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    Structure for shielding conductors
    1.
    发明授权
    Structure for shielding conductors 失效
    屏蔽导线结构

    公开(公告)号：US5345105A

    公开(公告)日：1994-09-06

    申请号：US103362

    申请日：1993-08-02

    申请人： Shih-Wei Sun ,  Yasunobu Kosa ,  John R. Yeargain

    发明人： Shih-Wei Sun ,  Yasunobu Kosa ,  John R. Yeargain

    IPC分类号： H01L23/522 ,  H01L23/552 ,  H01L23/58 ,  H01L23/34 ,  H01L25/04

    CPC分类号： H01L23/585 ,  H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  Y10S438/901

    摘要： A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions. A shielding conductive layer (20) is formed overlying dielectric layer (18) and at least partially fills the recessed regions to shield the electrically isolated conductive regions from each another.

    摘要翻译： 一种屏蔽结构（10）及其形成方法。 屏蔽结构（10）具有基板（12）。 第一介电层（14）覆盖在基板（12）上。 形成覆盖在电介质层（14）上的导电层（16）被图案化，并被蚀刻以与导电层（16）形成电隔离的导电区域。 电绝缘的导电区域具有侧壁，并且导电层（16）的蚀刻暴露介电层（14）的部分。 电介质层（14）的暴露部分被蚀刻以形成电介质层（14）的沟槽部分。 形成第二介电层（18），覆盖电隔离的导电区域（包括侧壁）并覆盖沟槽部分以形成分离电隔离导电区域的凹陷区域。 屏蔽导电层（20）形成在覆盖介电层（18）上并且至少部分地填充凹陷区域以将电隔离的导电区域彼此隔离。

    Process for forming a structure which electrically shields conductors
    2.
    发明授权
    Process for forming a structure which electrically shields conductors 失效
    用于形成电屏蔽导体的结构的方法

    公开(公告)号：US5262353A

    公开(公告)日：1993-11-16

    申请号：US829837

    申请日：1992-02-03

    申请人： Shih-Wei Sun ,  Yasunobu Kosa ,  John R. Yeargain

    发明人： Shih-Wei Sun ,  Yasunobu Kosa ,  John R. Yeargain

    IPC分类号： H01L23/522 ,  H01L23/552 ,  H01L23/58 ,  H01L21/44 ,  H01L21/48

    CPC分类号： H01L23/585 ,  H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  Y10S438/901

    摘要： A shielding structure (10) and method of formation. The shielding structure (10) has a substrate (12). A first dielectric layer (14) overlies the substrate (12). A conductive layer (16) is formed overlying the dielectric layer (14), is patterned, and is etched to form electrically isolated conductive regions from conductive layer (16). The electrically isolated conductive regions have sidewalls and the etching of conductive layer (16) exposes portions of dielectric layer (14). The exposed portions of dielectric layer (14) are etched to form trenched portions of dielectric layer (14). A second dielectric layer (18) is formed overlying the electrically isolated conductive regions, including the sidewalls, and overlying the trenched portions to create recessed regions that separate the electrically isolated conductive regions. A shielding conductive layer (20) is formed overlying dielectric layer (18) and at least partially fills the recessed regions to shield the electrically isolated conductive regions from each another.

    摘要翻译： 一种屏蔽结构（10）及其形成方法。 屏蔽结构（10）具有基板（12）。 第一介电层（14）覆盖在基板（12）上。 形成覆盖在电介质层（14）上的导电层（16）被图案化，并被蚀刻以与导电层（16）形成电隔离的导电区域。 电绝缘的导电区域具有侧壁，并且导电层（16）的蚀刻暴露介电层（14）的部分。 电介质层（14）的暴露部分被蚀刻以形成电介质层（14）的沟槽部分。 形成第二介电层（18），覆盖电隔离的导电区域（包括侧壁）并覆盖沟槽部分以形成分离电隔离导电区域的凹陷区域。 屏蔽导电层（20）形成在覆盖介电层（18）上并且至少部分地填充凹陷区域以将电隔离的导电区域彼此隔离。

    Method for forming a buried contact
    3.
    发明授权
    Method for forming a buried contact 失效
    用于形成掩埋触点的方法

    公开(公告)号：US5126285A

    公开(公告)日：1992-06-30

    申请号：US546974

    申请日：1990-07-02

    申请人： Yasunobu Kosa ,  John H. Sweeney ,  Scott S. Roth

    发明人： Yasunobu Kosa ,  John H. Sweeney ,  Scott S. Roth

    IPC分类号： H01L21/74

    CPC分类号： H01L21/743

    摘要： A buried contact in a semiconductor device is formed by forming an oxide layer on a surface of a semiconductor substrate. A heavily-doped polysilicon layer is formed over the oxide layer and selectively etched to leave a first portion of the polysilicon layer over the surface and remove a second portion of the polysilicon layer from over the surface. The remaining first portion of polysilicon has a vertical surface which is over the surface of the substrate. After this step there is oxide between the first portion of the polysilicon layer and the substrate. An isotropic etch is performed which removes a portion of the oxide between the first portion of the polysilicon layer and the substrate to leave a void between the first portion of the polysilicon layer and the surface of the substrate from the vertical surface of the first portion of the polysilicon to a predetermined distance from the vertical surface of the first portion of the polysilicon layer. A polysilicon layer is then deposited which fills the void with polysilicon. The polysilicon which is not filling the void is removed. An implant is then performed using the first portion of the polysilicon layer as a mask to form a first doped region in the substrate adjacent to the vertical surface of the first portion of the polysilicon layer. Because the polysilicon layer was doped, dopant from the first portion of the polysilicon layer migrates down through the polysilicon filling the void to form a second doped region in the substrate under the first portion of the polysilicon layer which merges with the first doped region in the substrate. This has the effect making electrical contact between the first portion of the polysilicon layer and the first doped region in the substrate and thus achieving a desired buried contact.

    摘要翻译： 通过在半导体衬底的表面上形成氧化层，形成半导体器件中的埋入触点。 在氧化物层上形成重掺杂的多晶硅层，并选择性地蚀刻以在多个表面上留下多晶硅层的第一部分，并从表面上去除多晶硅层的第二部分。 剩余的第一部分多晶硅具有在衬底的表面之上的垂直表面。 在该步骤之后，在多晶硅层的第一部分和衬底之间存在氧化物。 执行各向同性蚀刻，其除去多晶硅层的第一部分和基板之间的氧化物的一部分，以在多晶硅层的第一部分和基板的表面之间留下空隙，从第一部分的垂直表面 该多晶硅与多晶硅层的第一部分的垂直表面预定距离。 然后沉积多晶硅层，其用多晶硅填充空隙。 去除不填充空隙的多晶硅。 然后使用多晶硅层的第一部分作为掩模执行注入，以在与多晶硅层的第一部分的垂直表面相邻的衬底中形成第一掺杂区域。 由于多晶硅层被掺杂，所以来自多晶硅层的第一部分的掺杂剂向下延伸穿过填充空隙的多晶硅，以在多晶硅层的第一部分下方的衬底中形成第二掺杂区域，该第一掺杂区域与第一掺杂区域 基质。 这具有使多晶硅层的第一部分与衬底中的第一掺杂区域之间的电接触的效果，从而实现期望的埋入接触。

    Interconnection structure for semiconductor integrated circuits
    5.
    发明授权
    Interconnection structure for semiconductor integrated circuits 失效
    半导体集成电路的互连结构

    公开(公告)号：US4199778A

    公开(公告)日：1980-04-22

    申请号：US843366

    申请日：1977-10-19

    申请人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

    发明人： Toshiaki Masuhara ,  Tokumasa Yasui ,  Yoshio Sakai ,  Joh Nakajima ,  Yasunobu Kosa ,  Satoshi Meguro ,  Masaharu Kubo

    IPC分类号： H01L21/763 ,  H01L21/31 ,  H01L21/3205 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/52 ,  H01L23/532 ,  H01L29/04 ,  H01L23/48 ,  H01L29/44

    CPC分类号： H01L21/32155 ,  H01L21/76889 ,  H01L23/53271 ,  H01L2924/0002

    摘要： In a semiconductor integrated circuit having polycrystalline silicon interconnections and metal interconnections, a low resistance layer, containing impurities to a high concentration for the polycrystalline silicon interconnections, is formed in predetermined parts of an undoped polycrystalline silicon layer which is deposited on a first insulator film on a semiconductor substrate, a second insulator film is deposited on the polycrystalline silicon layer under the state under which the undoped parts are left at least around through-holes to be formed, and the metal interconnections at least parts of which run in a direction intersecting the polycrystalline silicon interconnections are provided on the second insulator film, the necessary contacts between the metal interconnections and the polycrystalline silicon interconnections being made through the through-holes provided in the second insulator film in correspondence with the intersecting parts of both the interconnections.

    摘要翻译： 在具有多晶硅互连和金属互连的半导体集成电路中，在未掺杂的多晶硅层的预定部分中形成在多晶硅互连中含有高浓度的杂质的低电阻层，其沉积在第一绝缘膜上 半导体衬底，第二绝缘膜沉积在多晶硅层上，在未被掺杂的部分至少留在待形成的通孔周围的状态下，并且其至少部分的金属互连在与 多晶硅互连设置在第二绝缘膜上，金属互连和多晶硅互连之间的必要接触通过设置在第二绝缘膜中的通孔形成，与两个互连的相交部分相对应。

    Method of manufacturing a semiconductor integrated circuit device
    8.
    发明授权
    Method of manufacturing a semiconductor integrated circuit device 失效
    制造半导体集成电路器件的方法

    公开(公告)号：US4373249A

    公开(公告)日：1983-02-15

    申请号：US186739

    申请日：1980-09-12

    申请人： Yasunobu Kosa ,  Kazuhiro Komori

    发明人： Yasunobu Kosa ,  Kazuhiro Komori

    IPC分类号： H01L27/112 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792 ,  H01L21/26

    CPC分类号： H01L21/28273 ,  H01L27/105 ,  H01L29/4916

    摘要： A semiconductor integrated circuit device, especially an EPROM (Electrically Programmable Read Only Memory) device which consists of an MIS type memory transistor portion having a floating gate electrode and a control gate electrode on said floating gate electrode, and of an MIS type transistor portion having a gate electrode is formed by patterning the same conductor layer as the floating gate electrode in the periphery of said MIS type memory transistor portion.

    摘要翻译： 一种半导体集成电路器件，特别是EPROM（电可编程只读存储器）器件，其由具有浮置栅电极的MIS型存储晶体管部分和在所述浮栅电极上的控制栅极电极组成，以及MIS型晶体管部分，其具有 通过在与所述MIS型存储晶体管部分周围的浮动栅极电极相同的导体层上形成栅电极。

    Semiconductor device having a static-random-access memory cell
    10.
    发明授权
    Semiconductor device having a static-random-access memory cell 失效
    具有静态随机存取存储单元的半导体器件

    公开(公告)号：US5739564A

    公开(公告)日：1998-04-14

    申请号：US460605

    申请日：1995-06-01

    申请人： Yasunobu Kosa ,  Howard C. Kirsch ,  Thomas F. McNelly ,  Frank Kelsey Baker

    发明人： Yasunobu Kosa ,  Howard C. Kirsch ,  Thomas F. McNelly ,  Frank Kelsey Baker

    IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/265 ,  H01L21/70

    CPC分类号： H01L27/11

    摘要： A static-random-access memory cell comprising floating node capacitors is disclosed. In one embodiment, the storage nodes acts as the first plates for the floating node capacitors, and a conductive member acts as the second plates for the floating node capacitors. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cell. In another embodiment, a conductive member acts as the second plates of a plurality of memory cells. The conductive member also electrically connects the second plates together, but is not electrically connected to other parts of the memory cells. Processes for forming the memory cells is also disclosed.

    摘要翻译： 公开了一种包括浮动节点电容器的静态随机存取存储器单元。 在一个实施例中，存储节点用作浮动节点电容器的第一板，并且导电构件用作浮动节点电容器的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 在另一个实施例中，导电构件用作多个存储单元的第二板。 导电构件还将第二板电连接在一起，但不与存储单元的其它部分电连接。 还公开了用于形成存储单元的工艺。