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公开(公告)号：US07260036B2
公开(公告)日：2007-08-21
申请号：US10389453
申请日：2003-03-14
IPC分类号： G11B7/0045
CPC分类号： G11B20/1403 , G11B7/00456 , G11B7/005 , G11B7/0062 , G11B2007/0006 , G11B2020/10879
摘要： A data processor compatible for use with a CD and a DVD includes a first modulation circuit for modulating recording data for recording on a CD to generate first modulated data. A second modulation circuit modulates recording data for recording on a DVD to generate second modulated data. A write signal generation circuit generates a first write signal, which is written to the CD, from the first modulated data, and a second write signal, which is written to the DVD, from the second modulated data. The write signal generation circuit is commonly used for the CD and the DVD to reduce the circuit area of the data processor.
摘要翻译： 与CD和DVD一起使用的数据处理器包括：第一调制电路，用于调制记录在CD上的数据，以产生第一调制数据。 第二调制电路调制用于在DVD上记录的记录数据，以产生第二调制数据。 写信号生成电路从第一调制数据生成写入CD的第一写信号和从第二调制数据写入DVD的第二写信号。 写入信号生成电路通常用于CD和DVD以减少数据处理器的电路面积。
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公开(公告)号：US07471128B2
公开(公告)日：2008-12-30
申请号：US10504607
申请日：2003-11-07
IPC分类号： H03L7/06
CPC分类号： G11B7/126 , G11B7/00456 , G11B7/0062 , G11B20/10 , H03K5/133 , H03K2005/00039 , H03L7/0805 , H03L7/0995 , H03L7/18 , H04L7/0337
摘要： A write strategy circuit (recording pulse generator) generates a recording pulse for controlling a laser output applied to an optical disc using data modulated by a DVD encoder or a CD encoder. A delay circuit delays delay subject signals by a predetermined amount to generate delay signals. A delay amount for the delay circuit is controlled by a delay amount control circuit. A logic circuit generates a recording pulse by logically synthesizing the delay signals. The delay amount control circuit includes a voltage controlled oscillator formed by connecting, in a ring-like manner, a plurality of delay elements having the same configuration as the delay elements included in the delay circuit. An output signal of the voltage controlled oscillator is locked at a point where a delay amount for each delay element becomes a fraction of an integer of one cycle of a reference clock signal.
摘要翻译： 写策略电路（记录脉冲发生器）使用由DVD编码器或CD编码器调制的数据产生用于控制施加到光盘的激光输出的记录脉冲。 延迟电路将延迟对象信号延迟预定量以产生延迟信号。 延迟电路的延迟量由延迟量控制电路控制。 逻辑电路通过逻辑合成延迟信号来产生记录脉冲。 延迟量控制电路包括通过以环状方式连接多个具有与延迟电路中包括的延迟元件相同配置的延迟元件形成的压控振荡器。 压控振荡器的输出信号被锁定在每个延迟元件的延迟量成为参考时钟信号的一个周期的整数的一部分的点处。
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公开(公告)号：US07089401B2
公开(公告)日：2006-08-08
申请号：US10373152
申请日：2003-02-24
IPC分类号： G06F12/00
CPC分类号： G11B20/10527 , G06F3/0611 , G06F3/0656 , G06F3/0658 , G06F3/0677 , G11B2020/10666 , G11B2020/10685 , G11B2020/10694 , G11B2220/2562
摘要： A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main data to or reads the main data from the buffer memory. An address generation circuit generates address data in accordance with a writing or reading head address of the main data provided from an external device. A counter counts the main data to generate a count value. An address skip control circuit skips the address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.
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公开(公告)号：US20050174911A1
公开(公告)日：2005-08-11
申请号：US10504607
申请日：2003-11-07
IPC分类号： G11B20/10 , G11B7/0045 , G11B7/006 , G11B7/125 , G11B20/14 , H03K5/00 , H03K5/13 , H03L7/08 , H03L7/081 , H03L7/099 , H03L7/18 , H04L7/033 , G11B5/09
CPC分类号： G11B7/126 , G11B7/00456 , G11B7/0062 , G11B20/10 , H03K5/133 , H03K2005/00039 , H03L7/0805 , H03L7/0995 , H03L7/18 , H04L7/0337
摘要： A write strategy circuit (recording pulse generator) generates a recording pulse for controlling a laser output applied to an optical disc using data modulated by a DVD encoder or a CD encoder. A delay circuit (220) delays delay subject signals S1 to S4 by a predetermined amount to generate delay signals D1 to D4. A delay amount for the delay circuit (220) is controlled by a delay amount control circuit (210). A logic circuit (300) generates a recording pulse by logically synthesizing the delay signals D1 to D4. The delay amount control circuit includes a voltage controlled oscillator formed by connecting, in a ring-like manner, a plurality of delay elements (211a) having the same configuration as the delay elements (221) included in the delay circuit. An output signal of the voltage controlled oscillator is locked at a point where a delay amount for each delay element (211a) becomes a fraction of an integer of one cycle of a reference clock signal.
摘要翻译： 写策略电路（记录脉冲发生器）使用由DVD编码器或CD编码器调制的数据产生用于控制施加到光盘的激光输出的记录脉冲。 延迟电路（220）将延迟对象信号S1至S4延迟预定量以产生延迟信号D 1至D 4。 延迟电路（220）的延迟量由延迟量控制电路（210）控制。 逻辑电路（300）通过逻辑合成延迟信号D 1至D 4产生记录脉冲。 延迟量控制电路包括通过以环状方式连接多个延迟元件（211a）形成的压控振荡器，该延迟元件具有与延迟电路中包括的延迟元件（221）相同的配置。 压控振荡器的输出信号被锁定在每个延迟元件（211a）的延迟量变成参考时钟信号的一个周期的整数的一部分的点处。
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公开(公告)号：US07289394B2
公开(公告)日：2007-10-30
申请号：US10673904
申请日：2003-09-29
IPC分类号： G11B21/08
CPC分类号： G11B27/3027 , G11B7/0045 , G11B7/007 , G11B20/1217 , G11B20/1426 , G11B27/034 , G11B27/10 , G11B27/24 , G11B2020/1232 , G11B2020/1274 , G11B2220/218 , G11B2220/2525 , G11B2220/2529 , G11B2220/2545 , G11B2220/2562
摘要： A data recording controller for properly adding data to a disc medium. The controller includes a data location counter for performing counting in synchronism with reproduction of data written to an optical disc. An LPP location counter performs counting in synchronization with reproduction of a disc address recorded to the optical disc. A detection circuit detects the difference between a data format address recorded to the optical disc and an optical disc address recorded to the optical disc from count values of the two counters. A control unit calculates a recording initiation address from the detected difference. A timing control circuit determines a timing for starting the recording of additional data from the recording initiation address.
摘要翻译： 一种用于将数据适当地添加到盘介质的数据记录控制器。 控制器包括用于与写入光盘的数据的再现同步地执行计数的数据位置计数器。 LPP位置计数器与记录到光盘的盘地址的再现同步地执行计数。 检测电路根据两个计数器的计数值检测记录在光盘上的数据格式地址与记录在光盘上的光盘地址之间的差异。 控制单元根据检测到的差计算记录起始地址。 定时控制电路从记录起始地址确定开始附加数据的记录的定时。
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公开(公告)号：US08179081B2
公开(公告)日：2012-05-15
申请号：US12772445
申请日：2010-05-03
IPC分类号： H02P8/00
CPC分类号： H02P8/16
摘要： A stepping motor includes two coils and has supply currents to the two coils with different phases so that a rotor is rotated by the two coils. During a period where one coil is in a high impedance state, an induced voltage generated at that coil is detected. An output control circuit controls the magnitude of motor drive current supplied to the two coils in accordance with the detected induced voltage state. Then, prior to entering the high impedance state from the drive state, a short-circuit period is provided for short circuiting both terminals of the coil.
摘要翻译： 步进电机包括两个线圈，并且具有不同相位的两个线圈的电源电流，使得转子由两个线圈旋转。 在一个线圈处于高阻抗状态的时段期间，检测到在该线圈处产生的感应电压。 输出控制电路根据检测到的感应电压状态来控制提供给两个线圈的电动机驱动电流的大小。 然后，在从驱动状态进入高阻抗状态之前，提供短路时间以使线圈的两个端子短路。
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公开(公告)号：US20100289444A1
公开(公告)日：2010-11-18
申请号：US12772445
申请日：2010-05-03
IPC分类号： H02P8/38
CPC分类号： H02P8/16
摘要： A stepping motor includes two coils and has supply currents to the two coils with different phases so that a rotor is rotated by the two coils. During a period where one coil is in a high impedance state, an induced voltage generated at that coil is detected. An output control circuit controls the magnitude of motor drive current supplied to the two coils in accordance with the detected induced voltage state. Then, prior to entering the high impedance state from the drive state, a short-circuit period is provided for short circuiting both terminals of the coil.
摘要翻译： 步进电机包括两个线圈，并且具有不同相位的两个线圈的电源电流，使得转子由两个线圈旋转。 在一个线圈处于高阻抗状态的时段期间，检测到在该线圈处产生的感应电压。 输出控制电路根据检测到的感应电压状态来控制提供给两个线圈的电动机驱动电流的大小。 然后，在从驱动状态进入高阻抗状态之前，提供短路时间以使线圈的两个端子短路。
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公开(公告)号：US07170331B2
公开(公告)日：2007-01-30
申请号：US11080685
申请日：2005-03-16
申请人： Toshiyuki Shutoku , Koji Hayashi
发明人： Toshiyuki Shutoku , Koji Hayashi
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00104
摘要： A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells.Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.
摘要翻译： 一种延迟电路，包括延迟线以延迟具有串联连接的多个延迟单元的输入信号; PLL电路，为延迟线提供延迟控制电压以控制延迟; 以及选择延迟单元的输出信号之一的第一选择器。 每个延迟单元包括串联连接的两级延迟反相器和连接到第一级的延迟反相器和第二级的延迟反相器的连接点的输出反相器。 第一级的延迟反相器的输入是前一延迟单元中的第二级的延迟反相器的输出信号，第一选择器作为延迟信号输出输出反相器或第二级的延迟反相器的输出信号 在延迟单元之一的阶段。
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公开(公告)号：US20050206425A1
公开(公告)日：2005-09-22
申请号：US11080685
申请日：2005-03-16
申请人： Toshiyuki Shutoku , Koji Hayashi
发明人： Toshiyuki Shutoku , Koji Hayashi
CPC分类号： H03H11/265 , H03K5/133 , H03K2005/00104
摘要： A delay circuit comprising a delay line to delay an input signal that has a plurality of delay cells connected in series; a PLL circuit that supplies the delay line with a delay control voltage to control the delay; and a first selector that selects one of output signals of the delay cells. Each of the delay cells comprises two stages of delay inverters connected in series and an output inverter connected to a connection point of the delay inverter of the first stage and the delay inverter of the second stage. Input into the delay inverter of the first stage is an output signal of the delay inverter of the second stage in the preceding delay cell, and the first selector outputs as a delayed signal an output signal of the output inverter or the delay inverter of the second stage in one of the delay cells.
摘要翻译： 一种延迟电路，包括延迟线以延迟具有串联连接的多个延迟单元的输入信号; PLL电路，为延迟线提供延迟控制电压以控制延迟; 以及选择延迟单元的输出信号之一的第一选择器。 每个延迟单元包括串联连接的两级延迟反相器和连接到第一级的延迟反相器和第二级的延迟反相器的连接点的输出反相器。 第一级的延迟反相器的输入是前一延迟单元中的第二级的延迟反相器的输出信号，第一选择器作为延迟信号输出输出反相器或第二级的延迟反相器的输出信号 在延迟单元之一的阶段。
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