Luminous composition and electroluminescent device comprising the same
    7.
    发明授权
    Luminous composition and electroluminescent device comprising the same 失效
    发光组合物和包含其的电致发光器件

    公开(公告)号:US6129986A

    公开(公告)日:2000-10-10

    申请号:US35856

    申请日:1998-03-06

    摘要: A luminous composition containing (A) at least one polymer selected from the group consisting of a fluoropolymer and a graft polymer which is a fluoropolymer to which a cyanoethylated acrylic monomer is grafted, (B) an alkoxysilane compound having a primary amine group, (C) an alcohol having 1 to 4 carbon atoms, (D) a fluorescent material powder, and (E) an organic solvent, which is suitable for the formation of a luminous layer of an electro-luminescent device, since it improves the adhesion of the luminous layer to a transparent electrode, and has practically satisfactory pot life and moisture resistance.

    摘要翻译: 一种含有(A)至少一种选自含氟聚合物和接枝聚合物的聚合物的发光组合物,所述聚合物是接枝氰基乙基化丙烯酸单体的含氟聚合物,(B)具有伯胺基的烷氧基硅烷化合物,(C )具有1至4个碳原子的醇,(D)荧光材料粉末和(E)适合于形成电致发光装置的发光层的有机溶剂,因为它改善了 发光层到透明电极,并且具有实际上令人满意的适用期和耐湿性。

    Process for producing tricyanoethylated pentaerythritol
    8.
    发明授权
    Process for producing tricyanoethylated pentaerythritol 失效
    制备三乙酰基季戊四醇的方法

    公开(公告)号:US5869732A

    公开(公告)日:1999-02-09

    申请号:US889937

    申请日:1997-07-10

    CPC分类号: C07C253/30

    摘要: An imporved process for producing tricyanoethylated pentaerythritol by selectively cyanoethylating only three hydroxy groups of pentaerythritol in a high yield such as 90 to 95%, involves reacting one mole of pentaerythritol with three mole of acrylonitrile by Micheal Addition Reaction in an alkaline aqueous solution in coexistence with an extraction solvent. The tricyanoethylated pentaerythritol has a high purity and is useful for production of a high dielectric polymer.

    摘要翻译: 通过选择性地氰基乙基化仅以三聚羟基的季戊四醇为高产率(如90-95%),制造三乙酰基季戊四醇的方法包括通过Micheal加成反应将一摩尔季戊四醇与三摩尔丙烯腈在碱性水溶液中共沸并与 提取溶剂。 三乙烯基化季戊四醇具有高纯度,可用于高介电聚合物的制备。

    Semiconductor memory device having plurality of equalizer control line
drivers
    9.
    发明授权
    Semiconductor memory device having plurality of equalizer control line drivers 失效
    具有多个均衡器控制线驱动器的半导体存储器件

    公开(公告)号:US6097648A

    公开(公告)日:2000-08-01

    申请号:US66579

    申请日:1998-04-24

    CPC分类号: G11C11/4097 G11C11/4094

    摘要: An equalizer control line BLEQ shared by all sense amplifiers SA in each row in each submat SM is connected to a first equalizer control line driver consisting of P-type MOS transistors installed at the left end of the submat SM and is connected to several second equalizer control line drivers 32 consisting of N-type MOS transistors installed by dividing in a cross area 16 of each row through which the equalizer control line BLEQ passes. In order to turn on the equalizers of the bit line pair connected to each sense amplifier S, the first equalizer control line driver is operated to drive the equalizer control line BLEQ to the H level potential. In order to turn off the equalizers of each bit line pair, the second equalizer control line drivers 32 are operated to drive the equalizer control line BLEQ to the L level potential. The first and second equalizer control line drivers are complementarily operated. One of them is driven, and the other is turned off (blocked).

    摘要翻译: 每个子矩阵SM中的每行中由所有读出放大器SA共享的均衡器控制线BLEQ连接到由安装在子矩阵SM的左端的P型MOS晶体管组成的第一均衡器控制线驱动器,并连接到多个第二均衡器 控制线驱动器32由通过在均衡器控制线BLEQ经过的每行的交叉区域16中分开安装的N型MOS晶体管组成。 为了接通连接到每个读出放大器S的位线对的均衡器,操作第一均衡器控制线驱动器以将均衡器控制线BLEQ驱动到H电平电位。 为了关闭每个位线对的均衡器,操作第二均衡器控制线驱动器32以将均衡器控制线BLEQ驱动为L电平电位。 第一和第二均衡器控制线驱动器互补操作。 其中一个被驱动,另一个被关闭(被阻止)。

    Semiconductor memory
    10.
    发明授权
    Semiconductor memory 有权
    半导体存储器

    公开(公告)号:US6038158A

    公开(公告)日:2000-03-14

    申请号:US189071

    申请日:1998-11-09

    CPC分类号: G11C7/06 G11C7/18

    摘要: The objective is to realize a semiconductor memory capable of avoiding an increase in the load of the sense amplifiers, easily realizing a large capacity and high integration of the memory, reducing the current consumption by the bit lines, and improving the access speed. Because the levels of the selection signal lines SHUS1, SHUE1, SHDS1, and SHDE1 are set by the control circuit, only one of the aforementioned four selection signal lines is selected at the time of memory access, other selection signal lines are held in unselect status, and the sense amplifiers in the sense amplifier bank SB1a and prescribed bit line pairs or extended bit line pairs are connected to each other by response in order to carry out read or write; thus, the load of the sense amplifiers can be reduced, and high speed, large capacity, and high integration can be achieved.

    摘要翻译: 目的是实现能够避免读出放大器的负载增加的半导体存储器,容易实现存储器的大容量和高集成度,减少位线的电流消耗,并提高存取速度。 由于选择信号线SHUS1,SHUE1,SHDS1和SHDE1的电平由控制电路设置,所以在存储器访问时仅选择上述四个选择信号线中的一个,其他选择信号线保持在取消选择状态 并且读出放大器组SB1a中的读出放大器和规定的位线对或扩展位线对通过响应彼此连接以便执行读或写; 因此能够降低读出放大器的负担,能够实现高速,大容量,高集成度。