公开(公告)号：US07028397B2

公开(公告)日：2006-04-18

申请号：US10159123

申请日：2002-06-03

申请人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

发明人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H05K3/34

CPC分类号： H01L24/83 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L2224/32245 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T156/1339

摘要： A semiconductor chip, substrate employing plural bonding steps to ensure complete bonding particularly of peripheral edges. Embodiments include placing an adhesive layer on a chip mounting substrate positioned on a first supporting device, pressing a semiconductor chip against the chip mounting substrate to bond the semiconductor chip temporarily to the chip mounting substrate temporarily bonded chip on a second supporting device, and applying chip to straighten warpage and to bond the chip entirely to the chip mounting substrate.

摘要翻译： 一种半导体芯片，采用多个接合步骤的基板，以确保特别是外围边缘的完全接合。 实施例包括将粘合剂层放置在位于第一支撑装置上的芯片安装基板上，将半导体芯片压靠在芯片安装基板上，将半导体芯片暂时地接合到芯片安装基板上，临时接合芯片在第二支撑装置上， 以矫正翘曲并将芯片完全粘合到芯片安装基板上。

公开(公告)号：US06965154B2

公开(公告)日：2005-11-15

申请号：US10810813

申请日：2004-03-29

申请人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

发明人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L25/18 ,  H01L23/495 ,  H01L23/50 ,  H01L25/065 ,  H01L25/07 ,  H01L29/00 ,  H01L23/06 ,  H01L23/34 ,  H01L23/48

CPC分类号： H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A semiconductor device and a manufacturing method thereof are provided with downsizing and densification achieved by reducing the thickness of the semiconductor device without increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed to overlap in the range of height with the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, a wire connects the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wire. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

摘要翻译： 通过减小半导体器件的厚度而不增加面积，提供了通过减小​​和致密化的半导体器件及其制造方法。 端子电极在平面图中布置在半导体芯片布置的区域的外部。 下半导体芯片放置成与端子电极在高度范围内重叠，上半导体芯片放置在下半导体芯片的上方，导线将上半导体芯片和下半导体芯片连接到端子电极，封装树脂封装 上下半导体芯片和导线。 封装树脂的底面与端子电极的底面共面。

公开(公告)号：US06995468B2

公开(公告)日：2006-02-07

申请号：US10798345

申请日：2004-03-12

申请人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

发明人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L23/34 ,  H01L21/48

CPC分类号： H01L24/83 ,  H01L21/2007 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/07802

摘要： In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.

摘要翻译： 在半导体器件制造方法中，将具有多个芯片的多个晶片承载并放置在管芯接合器中。 从多个晶片取出的芯片分别结合在一起，并通过结合层叠在堆叠中以形成芯片组件。 通过接合层将芯片组合到芯片焊盘。 因此，芯片接合器能够将由多个芯片组成的芯片组件接合到芯片焊盘，使得用于将多个芯片接合到管芯焊盘的管芯接合工艺的处理时间相对较短，半导体制造 设备以提高生产率生产半导体器件，规模相对较小，需要相对较低的设备投资。

公开(公告)号：US06737736B2

公开(公告)日：2004-05-18

申请号：US09892539

申请日：2001-06-28

申请人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

发明人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L23495

CPC分类号： H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A semiconductor device and a manufacturing method for downsizing and densification achieved by reducing the thickness of the semiconductor device without an increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed overlapping in height the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, wires connect the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wires. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

摘要翻译： 通过在不增加面积的情况下减小半导体器件的厚度来实现小型化和致密化的半导体器件和制造方法。 端子电极在平面图中布置在半导体芯片布置的区域的外部。 下半导体芯片与端子电极高度重叠，上半导体芯片放置在下半导体芯片的上方，将上下半导体芯片连接到端子电极，封装树脂封装上下半导体芯片， 电线 封装树脂的底面与端子电极的底面共面。

公开(公告)号：US06867507B2

公开(公告)日：2005-03-15

申请号：US10256006

申请日：2002-09-27

申请人： Tetsuya Uebayashi ,  Shunichi Abe ,  Naoki Izumi ,  Akira Yamazaki

发明人： Tetsuya Uebayashi ,  Shunichi Abe ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L21/52 ,  H01L23/495 ,  H01L23/50 ,  H01L23/544

CPC分类号： H01L23/49503 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： A section of predetermined geometry and area is provided on or in a die pad of a lead frame and taken as a mark to be used for checking the position of a semiconductor chip. If the semiconductor chip is placed outside an allowable range in the X direction, the semiconductor chip overlaps the mark, thereby changing the geometry of an observable portion (slanted portion) of the mark. By means of the change, a positional deviation of the semiconductor chip in the X direction can be ascertained. A positional deviation of the semiconductor chip in Y direction is determined, by observing whether or not an electrode is situated between extensions of sides of a certain portion of the section.

摘要翻译： 预定几何形状和面积的部分设置在引线框架的芯片焊盘上或芯片焊盘中，作为用于检查半导体芯片的位置的标记。 如果半导体芯片放置在X方向上的允许范围之外，则半导体芯片与标记重叠，从而改变标记的可观察部分（倾斜部分）的几何形状。 通过该变化，可以确定半导体芯片在X方向上的位置偏差。 通过观察电极是否位于该部分的某一部分的侧面的延伸部之间来确定半导体芯片在Y方向上的位置偏差。

公开(公告)号：US06784021B2

公开(公告)日：2004-08-31

申请号：US10090842

申请日：2002-03-06

申请人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

发明人： Shunichi Abe ,  Tetsuya Uebayashi ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L2144

CPC分类号： H01L24/83 ,  H01L21/2007 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/274 ,  H01L2224/32145 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2225/0651 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/07802

摘要： In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.

摘要翻译： 在半导体器件制造方法中，将具有多个芯片的多个晶片承载并放置在管芯接合器中。 从多个晶片取出的芯片分别结合在一起，并通过结合层叠在堆叠中以形成芯片组件。 通过接合层将芯片组合到芯片焊盘。 因此，芯片接合器能够将由多个芯片组成的芯片组件接合到芯片焊盘，使得用于将多个芯片接合到管芯焊盘的管芯接合工艺的处理时间相对较短，半导体制造 设备以提高生产率生产半导体器件，规模相对较小，需要相对较低的设备投资。

公开(公告)号：US20110039376A1

公开(公告)日：2011-02-17

申请号：US12853841

申请日：2010-08-10

申请人： Kunihiro Yamashita ,  Kazushi Hatauchi ,  Tetsuya Uebayashi

发明人： Kunihiro Yamashita ,  Kazushi Hatauchi ,  Tetsuya Uebayashi

IPC分类号： H01L21/60

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49503 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48647 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10157 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/3512

摘要： A high positional accuracy of a semiconductor chip is attained to stabilize the quality of a semiconductor device. In a die bonding process during assembly of an SIP, a microcomputer chip not required to have a high positional accuracy is picked up with a surface non-contact type collet and is die-bonded onto a first chip mounting portion, thereafter, an ASIC chip required to have a high positional accuracy is picked up with a surface contact type collet and die-bonded onto a second chip mounting portion. By thus using two types of collets properly, not only a high positional accuracy of the ASIC chip which has been die-bonded with the surface contact type collet is attained, but also the quality of the SIP is stabilized.

摘要翻译： 获得半导体芯片的高位置精度以稳定半导体器件的质量。 在组装SIP期间的芯片接合工艺中，使用表面非接触型夹头拾取不需要具有高位置精度的微型计算机芯片，并且芯片接合到第一芯片安装部分上，此后，ASIC芯片 需要具有高位置精度的表面接触型夹头并且芯片接合到第二芯片安装部分上。 通过适当地使用两种类型的夹头，不仅可以获得与表面接触型夹头进行芯片接合的ASIC芯片的高位置精度，而且稳定了SIP的质量。

公开(公告)号：US08318548B2

公开(公告)日：2012-11-27

申请号：US12853841

申请日：2010-08-10

申请人： Kunihiro Yamashita ,  Kazushi Hatauchi ,  Tetsuya Uebayashi

发明人： Kunihiro Yamashita ,  Kazushi Hatauchi ,  Tetsuya Uebayashi

IPC分类号： H01L21/00

CPC分类号： H01L24/06 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49503 ,  H01L23/49575 ,  H01L24/03 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/05647 ,  H01L2224/2919 ,  H01L2224/29339 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48647 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10157 ,  H01L2924/10161 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/3512

摘要： A high positional accuracy of a semiconductor chip is attained to stabilize the quality of a semiconductor device. In a die bonding process during assembly of an SIP, a microcomputer chip not required to have a high positional accuracy is picked up with a surface non-contact type collet and is die-bonded onto a first chip mounting portion, thereafter, an ASIC chip required to have a high positional accuracy is picked up with a surface contact type collet and die-bonded onto a second chip mounting portion. By thus using two types of collets properly, not only a high positional accuracy of the ASIC chip which has been die-bonded with the surface contact type collet is attained, but also the quality of the SIP is stabilized.

摘要翻译： 获得半导体芯片的高位置精度以稳定半导体器件的质量。 在组装SIP期间的芯片接合工艺中，使用表面非接触型夹头拾取不需要具有高位置精度的微型计算机芯片，并且芯片接合到第一芯片安装部分上，此后，ASIC芯片 需要具有高位置精度的表面接触型夹头并且芯片接合到第二芯片安装部分上。 通过适当地使用两种类型的夹头，不仅可以获得与表面接触型夹头进行芯片接合的ASIC芯片的高位置精度，而且稳定了SIP的质量。