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    Copper conductor
    3.
    发明申请
    Copper conductor 有权
    铜导体

    公开(公告)号：US20060006070A1

    公开(公告)日：2006-01-12

    申请号：US10887087

    申请日：2004-07-09

    申请人： Michael Lane ,  Stefanie Chiras ,  Terry Spooner ,  Robert Rosenberg ,  Daniel Edelstein

    发明人： Michael Lane ,  Stefanie Chiras ,  Terry Spooner ,  Robert Rosenberg ,  Daniel Edelstein

    IPC分类号： C25D1/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

    摘要翻译： 一种导电材料，包括：导电核心区域，其包含铜和0.001原子％至0.6原子％的选自铱，锇和铼的一种或多种金属; 和界面区域。 所述界面区域包含所述一种或多种金属的至少80原子％以上。 本发明还涉及一种制造导电材料的方法，包括：提供底层; 使底层与种子层接触，晶种层包含铜和一种或多种选自铱，锇和铼的金属; 在种子层上沉积包含铜的导电层，并且在足以在导电层中引起晶粒生长的温度下对导电层退火，同时最小化一种或多种合金金属从晶种层向导电层的迁移。 该方法还包括抛光导电层以提供抛光的铜表面材料，并且在一定温度下退火抛光的铜表面材料，以使一种或多种金属从晶种层迁移到抛光表面以提供接触的界面区域 具有铜导体核心区域。 界面区域和铜导体芯区域包括一种或多种金属。

    METHOD FOR FABRICATING BACK END OF THE LINE STRUCTURES WITH LINER AND SEED MATERIALS
    5.
    发明申请
    METHOD FOR FABRICATING BACK END OF THE LINE STRUCTURES WITH LINER AND SEED MATERIALS 有权
    用衬里和种子材料制作线结构的后端的方法

    公开(公告)号：US20070246792A1

    公开(公告)日：2007-10-25

    申请号：US11380074

    申请日：2006-04-25

    申请人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Shom Ponoth ,  Terry Spooner

    发明人： Chih-Chao Yang ,  Shyng-Tsong Chen ,  Shom Ponoth ,  Terry Spooner

    IPC分类号： H01L29/00 ,  H01L21/4763

    CPC分类号： H01L21/76846 ,  H01L21/76865

    摘要： A sputter-etching method employed to achieve a thinned down noble metal liner layer deposited on the surface or field of an intermediate back end of the line (BEOL) interconnect structure. The noble metal liner layer is substantially thinned down to a point where the effect of the noble metal has no significant effect in the chemical-mechanical polishing (CMP) process. The noble metal liner layer may be completely removed by sputter etching to facilitate effective planarization by chemical-mechanical polishing to take place.

    摘要翻译： 用于实现沉积在线（BEOL）互连结构的中间后端的表面或场上的减薄的贵金属衬里层的溅射蚀刻方法。 贵金属衬里层基本上变薄到贵金属的作用在化学机械抛光（CMP）工艺中没有显着影响的程度。 可以通过溅射蚀刻完全去除贵金属衬里层，以便通过化学机械抛光发生有效的平坦化。

    MAINTAINING UNIFORM CMP HARD MASK THICKNESS
    6.
    发明申请
    MAINTAINING UNIFORM CMP HARD MASK THICKNESS 有权
    维持均匀的CMP硬掩模厚度

    公开(公告)号：US20060043590A1

    公开(公告)日：2006-03-02

    申请号：US10711145

    申请日：2004-08-27

    申请人： Steven Shyng-Tsong Chen ,  Kaushik Kumar ,  Stephen Greco ,  Shom Ponoth ,  Terry Spooner ,  David Rath ,  Wei-Tsu Tseng

    发明人： Steven Shyng-Tsong Chen ,  Kaushik Kumar ,  Stephen Greco ,  Shom Ponoth ,  Terry Spooner ,  David Rath ,  Wei-Tsu Tseng

    IPC分类号： H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76832 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A chemical mechanical polishing (CMP) step is used to remove excess conductive material (e.g., Cu) overlying a low-k or ultralow-k interlevel dielectric layer (ILD) layer having trenches filled with conductive material, for a damascene interconnect structure. A reactive ion etch (RIE) or a Gas Cluster Ion Beam (GCIB) process is used to remove a portion of a liner which is atop a hard mask. A wet etch step is used to remove an oxide portion of the hard mask overlying the ILD, followed by a final touch-up Cu CMP (CMP) step which chops the protruding Cu patterns off and lands on the SiCOH hard mask. In this manner, processes used to remove excess conductive material substantially do not affect the portion of the hard mask overlying the interlevel dielectric layer.

    摘要翻译： 化学机械抛光（CMP）步骤用于去除覆盖在具有填充有导电材料的沟槽的低k或超低k层间介质层（ILD）层上的过剩导电材料（例如Cu），用于镶嵌互连结构。 使用反应离子蚀刻（RIE）或气体簇离子束（GCIB）方法去除位于硬掩模顶部的衬垫的一部分。 使用湿蚀刻步骤去除覆盖在ILD上的硬掩模的氧化物部分，随后是最后的上覆Cu CMP（CMP）步骤，其将突出的Cu图案切掉并落在SiCOH硬掩模上。 以这种方式，用于去除过量的导电材料的工艺基本上不影响覆盖层间电介质层的硬掩模的部分。

    GCIB LINER AND HARDMASK REMOVAL PROCESS
    8.
    发明申请
    GCIB LINER AND HARDMASK REMOVAL PROCESS 有权
    GCIB LINER和HARDMASK拆卸过程

    公开(公告)号：US20070117342A1

    公开(公告)日：2007-05-24

    申请号：US11164423

    申请日：2005-11-22

    申请人： Shyng-Tsong Chen ,  John Fitzsimmons ,  Shom Ponoth ,  Terry Spooner

    发明人： Shyng-Tsong Chen ,  John Fitzsimmons ,  Shom Ponoth ,  Terry Spooner

    IPC分类号： H01L21/76

    CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/7684

    摘要： A method comprises depositing a dielectric film layer, a hard mask layer, and a patterned photo resist layer on a substrate. The method further includes selectively etching the dielectric film layer to form sub-lithographic features by reactive ion etch processing and depositing a barrier metal layer and a copper layer. The method further includes etching the barrier metal layer and hard mask layer by gas cluster ion beam (GCIB) processing.

    摘要翻译： 一种方法包括在衬底上沉积电介质膜层，硬掩模层和图案化光刻胶层。 该方法还包括通过反应离子蚀刻处理选择性地蚀刻电介质膜层以形成亚光刻特征，并沉积阻挡金属层和铜层。 该方法还包括通过气体簇离子束（GCIB）处理蚀刻阻挡金属层和硬掩模层。

    METHOD OF MAKING A SEMICONDUCTOR STRUCTURE WITH A PLATING ENHANCEMENT LAYER
    9.
    发明申请
    METHOD OF MAKING A SEMICONDUCTOR STRUCTURE WITH A PLATING ENHANCEMENT LAYER 有权
    用镀层增强层制作半导体结构的方法

    公开(公告)号：US20070166996A1

    公开(公告)日：2007-07-19

    申请号：US11306930

    申请日：2006-01-17

    申请人： Shom Ponoth ,  Steven Chen ,  John Fitzsimmons ,  Terry Spooner

    发明人： Shom Ponoth ,  Steven Chen ,  John Fitzsimmons ,  Terry Spooner

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76873 ,  H01L21/7688 ,  H01L2221/1089

    摘要： Disclosed is a method of making a semiconductor structure, wherein the method includes forming an interlayer dielectric (ILD) layer on a semiconductor layer, forming a conductive plating enhancement layer (PEL) on the ILD, patterning the ILD and PEL, depositing a seed layer into the pattern formed by the ILD and PEL, and then plating copper on the seed layer. The PEL serves to decrease the resistance across the wafer so to facilitate the plating of the copper. The PEL preferably is an optically transparent and conductive layer.

    摘要翻译： 公开了一种半导体结构的制造方法，其特征在于，在半导体层上形成层间电介质层（ILD）层，在ILD上形成导电性电镀增强层（PEL），图案化ILD和PEL， 进入由ILD和PEL形成的图案，然后在种子层上镀铜。 PEL用于降低晶片上的电阻，以便于镀铜。 PEL优选是光学透明且导电的层。

    Novel structure and method for metal integration
    10.
    发明申请
    Novel structure and method for metal integration 有权
    金属一体化的新型结构与方法

    公开(公告)号：US20070205482A1

    公开(公告)日：2007-09-06

    申请号：US11364953

    申请日：2006-03-01

    申请人： Chih-Chao Yang ,  Terry Spooner ,  Oscar Straten

    发明人： Chih-Chao Yang ,  Terry Spooner ,  Oscar Straten

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76831 ,  H01L21/02063 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/32131 ,  H01L21/76805 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An interconnect structure including a gouging feature at the bottom of one of the via openings and a method of forming the same are provided. In accordance with the present invention, the method of forming the interconnect structure does not disrupt the coverage of the deposited diffusion barrier in the overlying line opening, nor does it introduce damages caused by Ar sputtering into the dielectric material including the via and line openings. In accordance with the present invention, such an interconnect structure contains a diffusion barrier layer only within the via opening, but not in the overlying line opening. This feature enhances both mechanical strength and diffusion property around the via opening areas without decreasing volume fraction of conductor inside the line openings. In accordance with the present invention, such an interconnect structure is achieved by providing the gouging feature in the bottom of the via opening prior to formation of the line opening and deposition of the diffusion barrier in said line opening.

    摘要翻译： 提供一种互连结构，其包括在一个通孔开口的底部的气泡特征及其形成方法。 根据本发明，形成互连结构的方法不会破坏上覆线路开口中沉积的扩散阻挡层的覆盖，也不会引起由Ar溅射引起的包括通孔和线路开口的电介质材料的损伤。 根据本发明，这种互连结构仅在通孔开口内包含扩散阻挡层，但不包括在上覆开口中。 该特征增强了通孔开口区域周围的机械强度和扩散性能，而不会降低线路开口内导体的体积分数。 根据本发明，这种互连结构是通过在形成线路开口和在所述线路开口中的扩散阻挡层的沉积之前提供通孔开口的底部中的气流特征来实现的。