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    Copper conductor
    2.
    发明申请
    Copper conductor 有权
    铜导体

    公开(公告)号：US20060006070A1

    公开(公告)日：2006-01-12

    申请号：US10887087

    申请日：2004-07-09

    申请人： Michael Lane ,  Stefanie Chiras ,  Terry Spooner ,  Robert Rosenberg ,  Daniel Edelstein

    发明人： Michael Lane ,  Stefanie Chiras ,  Terry Spooner ,  Robert Rosenberg ,  Daniel Edelstein

    IPC分类号： C25D1/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： C25D5/10 ,  C25D5/50 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53233 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A conducting material comprising: a conducting core region comprising copper and from 0.001 atomic percent to 0.6 atomic percent of one or more metals selected from iridium, osmium and rhenium; and an interfacial region. The interfacial region comprises at least 80 atomic percent or greater of the one or more metals. The invention is also directed to a method of making a conducting material comprising: providing an underlayer; contacting the underlayer with a seed layer, the seed layer comprising copper and one or more metals selected from iridium, osmium and rhenium; depositing a conducting layer comprising copper on the seed layer, and annealing the conducting layer at a temperature sufficient to cause grain growth in the conducting layer, yet minimize the migration of the one or more alloy metals from the seed layer to the conducting layer. The method further comprises polishing the conducting layer to provide a polished copper surface material, and annealing the polished copper surface material at a temperature to cause migration of the one or more metals from the seed layer to the polished surface to provide an interfacial region in contact with a copper conductor core region. The interfacial region and the copper conductor core region comprise the one or more metals.

    摘要翻译： 一种导电材料，包括：导电核心区域，其包含铜和0.001原子％至0.6原子％的选自铱，锇和铼的一种或多种金属; 和界面区域。 所述界面区域包含所述一种或多种金属的至少80原子％以上。 本发明还涉及一种制造导电材料的方法，包括：提供底层; 使底层与种子层接触，晶种层包含铜和一种或多种选自铱，锇和铼的金属; 在种子层上沉积包含铜的导电层，并且在足以在导电层中引起晶粒生长的温度下对导电层退火，同时最小化一种或多种合金金属从晶种层向导电层的迁移。 该方法还包括抛光导电层以提供抛光的铜表面材料，并且在一定温度下退火抛光的铜表面材料，以使一种或多种金属从晶种层迁移到抛光表面以提供接触的界面区域 具有铜导体核心区域。 界面区域和铜导体芯区域包括一种或多种金属。

    WRITING TO MEMORY USING SHARED ADDRESS BUSES
    10.
    发明申请
    WRITING TO MEMORY USING SHARED ADDRESS BUSES 失效
    使用共享地址记录写入记忆

    公开(公告)号：US20110078387A1

    公开(公告)日：2011-03-31

    申请号：US12568125

    申请日：2009-09-28

    申请人： Stefanie Chiras ,  Michele Franceschini ,  John P. Karidis ,  Luis A. Lastras ,  Mayank Sharma

    发明人： Stefanie Chiras ,  Michele Franceschini ,  John P. Karidis ,  Luis A. Lastras ,  Mayank Sharma

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1684 ,  G11C7/10 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1075

    摘要： Techniques for writing to memory using shared address buses. A memory device that includes a plurality of memory arrays connected to a common address bus, the common address bus used to broadcast memory addresses simultaneously to the plurality of memory arrays. Each memory array includes a plurality of memory locations and circuitry for: receiving the broadcasted memory addresses from the address bus; selecting a memory address in the memory array from a list of most recent memory addresses received from the address bus; and performing a memory access at the selected memory address, such that at a given point in time at least two of the memory arrays perform the memory access at a different broadcasted address when the memory access is a write.

    摘要翻译： 使用共享地址总线写入存储器的技术。 一种存储器件，包括连接到公共地址总线的多个存储器阵列，所述公共地址总线用于同时向所述多个存储器阵列广播存储器地址。 每个存储器阵列包括多个存储器位置和电路，用于：从地址总线接收广播的存储器地址; 从从地址总线接收的最近的存储器地址的列表中选择存储器阵列中的存储器地址; 以及在所选择的存储器地址处执行存储器访问，使得在给定时间点，当存储器访问是写入时，至少两个存储器阵列在不同的广播地址处执行存储器访问。