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    Etching a metal hard mask for an integrated circuit structure
    1.
    发明授权
    Etching a metal hard mask for an integrated circuit structure 失效
    刻蚀集成电路结构的金属硬掩模

    公开(公告)号：US06930048B1

    公开(公告)日：2005-08-16

    申请号：US10246844

    申请日：2002-09-18

    申请人： SiYi Li ,  S.M. Rega Sadjadi ,  Sean S. Kang ,  Tri Le ,  Bi-Ming Yen ,  Scott Briggs

    发明人： SiYi Li ,  S.M. Rega Sadjadi ,  Sean S. Kang ,  Tri Le ,  Bi-Ming Yen ,  Scott Briggs

    IPC分类号： H01L21/302 ,  H01L21/3213 ,  H01L21/768

    CPC分类号： H01L21/32136 ,  H01L21/76802 ,  H01L21/76832

    摘要： The invention is a method of etching an integrated circuit (IC) structure that includes a metal hard mask layer. The etching of the metal hard mask layer is performed by first feeding a gas mixture comprising a fluorine containing gas and oxygen (O2) gas to a reactor. The method then proceeds to generate a plasma that etches the metal hard mask layer. The method can be applied to either performing a via etch or a trench etch. Additionally, the invention teaches the removal of a photoresist layer without affecting the metal hard mask layer.

    摘要翻译： 本发明是一种蚀刻包含金属硬掩模层的集成电路（IC）结构的方法。 金属硬掩模层的蚀刻通过首先将包含含氟气体和氧气（O 2/2））的气体混合到反应器中来进行。 然后该方法进行以产生蚀刻金属硬掩模层的等离子体。 该方法可以应用于执行通孔蚀刻或沟槽蚀刻。 另外，本发明教导了去除光致抗蚀剂层而不影响金属硬掩模层。

    UNIFORM ETCH SYSTEM
    3.
    发明申请
    UNIFORM ETCH SYSTEM 有权
    均匀蚀刻系统

    公开(公告)号：US20080210377A1

    公开(公告)日：2008-09-04

    申请号：US12055212

    申请日：2008-03-25

    申请人： Dean J. Larson ,  Babak Kadkhodayan ,  Di Wu ,  Kenji Takeshita ,  Bi-Ming Yen ,  Xingcai Su ,  William M. Denty ,  Peter Loewenhardt

    发明人： Dean J. Larson ,  Babak Kadkhodayan ,  Di Wu ,  Kenji Takeshita ,  Bi-Ming Yen ,  Xingcai Su ,  William M. Denty ,  Peter Loewenhardt

    IPC分类号： C23F1/08

    CPC分类号： H01L21/67017

    摘要： Etching a layer over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to the outer zone within the plasma processing chamber, where the outer zone surrounds the inner zone and the first gas is different than the second gas. Plasmas are simultaneously generated from the first gas and second gas. The layer is etched, where the layer is etched by the plasmas from the first gas and second gas.

    摘要翻译： 提供了在衬底上蚀刻一层。 将基板放置在等离子体处理室中。 第一气体被提供到等离子体处理室内的内部区域。 第二气体被提供到等离子体处理室内的外部区域，其中外部区域围绕内部区域并且第一气体不同于第二气体。 从第一气体和第二气体同时产生等离子体。 蚀刻该层，其中该层被来自第一气体和第二气体的等离子体蚀刻。

    Uniform etch system
    4.
    发明授权
    Uniform etch system 有权
    均匀刻蚀系统

    公开(公告)号：US07371332B2

    公开(公告)日：2008-05-13

    申请号：US10642083

    申请日：2003-08-14

    申请人： Dean J. Larson ,  Babak Kadkhodayan ,  Di Wu ,  Kenji Takeshita ,  Bi-Ming Yen ,  Xingcai Su ,  William M. Denty, Jr. ,  Peter Loewenhardt

    发明人： Dean J. Larson ,  Babak Kadkhodayan ,  Di Wu ,  Kenji Takeshita ,  Bi-Ming Yen ,  Xingcai Su ,  William M. Denty, Jr. ,  Peter Loewenhardt

    IPC分类号： H01L21/306

    CPC分类号： H01L21/67017

    摘要： Etching a layer over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to the outer zone within the plasma processing chamber, where the outer zone surrounds the inner zone and the first gas is different than the second gas. Plasmas are simultaneously generated from the first gas and second gas. The layer is etched, where the layer is etched by the plasmas from the first gas and second gas.

    摘要翻译： 提供了在衬底上蚀刻一层。 将基板放置在等离子体处理室中。 第一气体被提供到等离子体处理室内的内部区域。 第二气体被提供到等离子体处理室内的外部区域，其中外部区域围绕内部区域并且第一气体不同于第二气体。 从第一气体和第二气体同时产生等离子体。 蚀刻该层，其中该层被来自第一气体和第二气体的等离子体蚀刻。

    IN-SITU PHOTORESIST STRIP DURING PLASMA ETCHING OF ACTIVE HARD MASK
    7.
    发明申请
    IN-SITU PHOTORESIST STRIP DURING PLASMA ETCHING OF ACTIVE HARD MASK 有权
    活动硬掩模等离子体蚀刻中的现场光电子条纹

    公开(公告)号：US20130001754A1

    公开(公告)日：2013-01-03

    申请号：US13607390

    申请日：2012-09-07

    申请人： Sangjun Cho ,  Tom Choi ,  Taejoon Han ,  Sean Kang ,  Prabhakara Gopaladasu ,  Bi-Ming Yen

    发明人： Sangjun Cho ,  Tom Choi ,  Taejoon Han ,  Sean Kang ,  Prabhakara Gopaladasu ,  Bi-Ming Yen

    IPC分类号： H01L21/308 ,  H01L21/3065 ,  H01L29/02

    CPC分类号： H01L21/3081 ,  G03F7/427 ,  H01L21/31138 ,  H01L21/32139

    摘要： A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.

    摘要翻译： 提供了一种用于蚀刻硅层中的特征的方法。 在硅层上形成硬掩模层。 在硬掩模层上形成光致抗蚀剂层。 打开硬掩模层。 通过提供剥离气体来剥离光致抗蚀剂层; 通过提供高频RF功率和低频RF功率与剥离气体形成等离子体，其中低频RF功率具有小于50瓦的功率; 并且当剥离光致抗蚀剂层时停止剥离气体。 打开硬掩模层和剥离光致抗蚀剂层在相同的室中进行。

    Methods for the optimization of substrate etching in a plasma processing system
    8.
    发明申请
    Methods for the optimization of substrate etching in a plasma processing system 有权
    在等离子体处理系统中优化衬底蚀刻的方法

    公开(公告)号：US20050205519A1

    公开(公告)日：2005-09-22

    申请号：US10804430

    申请日：2004-03-19

    申请人： Jisoo Kim ,  Binet Worsham ,  Bi-Ming Yen ,  Peter Loewenhardt

    发明人： Jisoo Kim ,  Binet Worsham ,  Bi-Ming Yen ,  Peter Loewenhardt

    IPC分类号： B44C1/22 ,  C03C15/00 ,  C23F1/00 ,  H01L21/302 ,  H01L21/311 ,  H01L21/768

    CPC分类号： H01L21/31144 ,  H01L21/76811 ,  H01L21/76813

    摘要： A method of etching a substrate in a plasma processing system is disclosed. The substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer. The method includes alternatively etching the substrate with a first etchant and a second etchant, wherein the first etchant has a low selectivity to a first hard mask material of the first hard mask layer, a third hard mask material of the a third hard mask layer, and a first barrier layer material of the first barrier layer, but a high selectivity to a second hard mask material of the second hard mask layer; and wherein the second etchant has a high selectivity to the first hard mask material of the first hard mask layer, the third hard mask material of the third hard mask layer, and the first barrier layer material of the first barrier layer, and the first etchant has a low selectivity to the second hard mask material of the second hard mask layer.

    摘要翻译： 公开了一种在等离子体处理系统中蚀刻衬底的方法。 衬底具有半导体层，设置在半导体层上方的第一势垒层，设置在第一阻挡层上方的低k层，设置在低k层上方的第三硬掩模层; 设置在第三硬掩模层之上的第二硬掩模层，以及设置在第二硬掩模层上方的第一硬掩模层。 所述方法包括用第一蚀刻剂和第二蚀刻剂替代地蚀刻所述衬底，其中所述第一蚀刻剂对所述第一硬掩模层的第一硬掩模材料具有低选择性，所述第三硬掩模层的第三硬掩模材料， 和第一阻挡层的第一阻挡层材料，但对第二硬掩模层的第二硬掩模材料具有高选择性; 并且其中第二蚀刻剂对第一硬掩模层的第一硬掩模材料，第三硬掩模层的第三硬掩模材料和第一阻挡层的第一阻挡层材料和第一蚀刻剂具有高选择性 对第二硬掩模层的第二硬掩模材料具有低选择性。

    Configurable plasma volume etch chamber
    9.
    发明授权
    Configurable plasma volume etch chamber 有权
    可配置等离子体体积蚀刻室

    公开(公告)号：US06527911B1

    公开(公告)日：2003-03-04

    申请号：US09895537

    申请日：2001-06-29

    申请人： Bi-Ming Yen ,  Tuqiang Ni ,  Lumin Li ,  David Hemker

    发明人： Bi-Ming Yen ,  Tuqiang Ni ,  Lumin Li ,  David Hemker

    IPC分类号： H05H100

    CPC分类号： H01J37/32623 ,  H01J37/32568

    摘要： A plasma processing chamber is provided. The plasma processing chamber includes a bottom electrode configured to support a substrate and a top electrode located over the bottom electrode. The plasma processing chamber further includes a plasma confinement assembly designed to transition between a closed orientation and an open orientation. In the closed orientation, the plasma confinement assembly defines a first volume for plasma during processing, and in the open orientation, the plasma confinement assembly defines a second volume for plasma during processing which is larger than the first volume.

    摘要翻译： 提供等离子体处理室。 等离子体处理室包括配置成支撑基板的底部电极和位于底部电极上方的顶部电极。 等离子体处理室还包括设计成在闭合取向和开放取向之间转变的等离子体限制组件。 在封闭取向中，等离子体限制组件在处理期间限定等离子体的第一容积，并且在开放取向中，等离子体限制组件在处理期间限定大于第一容积的等离子体的第二容积。

    In-situ photoresist strip during plasma etching of active hard mask
    10.
    发明授权
    In-situ photoresist strip during plasma etching of active hard mask 有权
    在等离子体蚀刻活性硬掩模时的原位光刻胶条

    公开(公告)号：US08912633B2

    公开(公告)日：2014-12-16

    申请号：US13607390

    申请日：2012-09-07

    申请人： Sangjun Cho ,  Tom Choi ,  Taejoon Han ,  Sean Kang ,  Prabhakara Gopaladasu ,  Bi-Ming Yen

    发明人： Sangjun Cho ,  Tom Choi ,  Taejoon Han ,  Sean Kang ,  Prabhakara Gopaladasu ,  Bi-Ming Yen

    IPC分类号： H01L21/3213 ,  H01L21/311 ,  G03F7/42 ,  H01L21/308

    CPC分类号： H01L21/3081 ,  G03F7/427 ,  H01L21/31138 ,  H01L21/32139

    摘要： A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.

    摘要翻译： 提供了一种用于蚀刻硅层中的特征的方法。 在硅层上形成硬掩模层。 在硬掩模层上形成光致抗蚀剂层。 打开硬掩模层。 通过提供剥离气体来剥离光致抗蚀剂层; 通过提供高频RF功率和低频RF功率与剥离气体形成等离子体，其中低频RF功率具有小于50瓦的功率; 并且当剥离光致抗蚀剂层时停止剥离气体。 打开硬掩模层和剥离光致抗蚀剂层在相同的室中进行。