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    Package on package structure and fabrication method thereof
    1.
    发明授权
    Package on package structure and fabrication method thereof 有权
    封装结构及其制造方法

    公开(公告)号：US09362217B2

    公开(公告)日：2016-06-07

    申请号：US14290145

    申请日：2014-05-29

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Pang-Chun Lin ,  Wei-Ping Wang ,  Chun-Yuan Li ,  Shao-tzu Tang ,  Ying-Chou Tsai

    IPC: H01L21/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10

    CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield.

    Abstract translation: 公开了一种用于制造POP结构的方法。 首先，提供第一封装，其具有：介电层; 嵌入介电层中并从电介质层的上表面和下表面露出的堆叠电路层; 多个导电柱和设置在电介质层的上表面上并电连接到堆叠电路层的半导体芯片; 以及密封剂，其形成在所述电介质层的上表面上，用于封装所述半导体芯片和所述导电柱，并具有用于暴露所述导电柱的顶端的多个开口。 然后，第二包装被设置在密封剂上并电连接到导电柱。 导电柱的形成有助于减小密封剂的开口的深度，从而减少制造时间并提高生产效率和产率。

    CIRCUIT STRUCTURE AND FABRICATION METHOD THEREOF
    2.
    发明申请
    CIRCUIT STRUCTURE AND FABRICATION METHOD THEREOF 有权
    电路结构及其制造方法

    公开(公告)号：US20150366060A1

    公开(公告)日：2015-12-17

    申请号：US14453952

    申请日：2014-08-07

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Shao-tzu Tang ,  Ying-Chou Tsai

    IPC: H05K1/11 ,  H05K3/40

    CPC classification number: H05K3/0014 ,  H05K1/116 ,  H05K2201/09118 ,  H05K2201/09545 ,  H05K2201/09563 ,  Y10T29/49167

    Abstract: A circuit structure is provided, which includes a plurality of conductive posts, and a plurality of first and second conductive pads formed on two opposite end surfaces of the conductive posts, respectively. A length of each of the first conductive pads is greater than a width of the first conductive pad so as to reduce an occupation area of the first conductive pad along the width and increase a distance between adjacent first conductive pads, thereby increasing the wiring density and meeting the wiring demand.

    Abstract translation: 提供了一种电路结构，其包括多个导电柱，以及分别形成在导电柱的两个相对端表面上的多个第一和第二导电垫。 每个第一导电焊盘的长度大于第一导电焊盘的宽度，以便沿着宽度减小第一导电焊盘的占用面积并且增加相邻的第一导电焊盘之间的距离，由此增加布线密度和 满足布线需求。

    PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
    3.
    发明申请
    PACKAGE ON PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF 有权
    包装结构及其制造方法

    公开(公告)号：US20150091150A1

    公开(公告)日：2015-04-02

    申请号：US14290145

    申请日：2014-05-29

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Pang-Chun Lin ,  Wei-Ping Wang ,  Chun-Yuan Li ,  Shao-tzu Tang ,  Ying-Chou Tsai

    IPC: H01L25/11 ,  H01L25/00

    CPC classification number: H01L23/49811 ,  H01L23/49827 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A method for fabricating a POP structure is disclosed. First, a first package is provided, which has: a dielectric layer; a stacked circuit layer embedded in the dielectric layer and exposed from upper and lower surfaces of the dielectric layer; a plurality of conductive posts and a semiconductor chip disposed on the upper surface of the dielectric layer and electrically connected to the stacked circuit layer; and an encapsulant formed on upper surface of the dielectric layer for encapsulating the semiconductor chip and the conductive posts and having a plurality of openings for exposing top ends of the conductive posts. Then, a second package is disposed on the encapsulant and electrically connected to the conductive posts. The formation of the conductive posts facilitates to reduce the depth of the openings of the encapsulant, thereby reducing the fabrication time and increasing the production efficiency and yield.

    Abstract translation: 公开了一种用于制造POP结构的方法。 首先，提供第一封装，其具有：介电层; 嵌入介电层中并从电介质层的上表面和下表面露出的堆叠电路层; 多个导电柱和设置在电介质层的上表面上并电连接到堆叠电路层的半导体芯片; 以及密封剂，其形成在所述电介质层的上表面上，用于封装所述半导体芯片和所述导电柱，并具有用于暴露所述导电柱的顶端的多个开口。 然后，第二包装被设置在密封剂上并电连接到导电柱。 导电柱的形成有助于减小密封剂的开口的深度，从而减少制造时间并提高生产效率和产率。

    PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF
    5.
    发明申请
    PACKAGING SUBSTRATE AND FABRICATION METHOD THEREOF 有权
    包装基板及其制造方法

    公开(公告)号：US20150305162A1

    公开(公告)日：2015-10-22

    申请号：US14461828

    申请日：2014-08-18

    Applicant: Siliconware Precision Industries Co., Ltd.

    Inventor： Shao-tzu Tang ,  Chi-Ching Ho ,  Ying-Chou Tsai

    IPC: H05K1/18 ,  H05K3/10 ,  H05K1/11

    CPC classification number: H05K1/186 ,  H01L23/49822 ,  H01L23/50 ,  H01L28/40 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/10 ,  H05K3/42 ,  H05K2201/10015 ,  H05K2203/0733 ,  H01L2924/00

    Abstract: A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.

    Abstract translation: 提供一种封装基板的制造方法，其包括以下步骤：在载体上形成第一导电部分; 在每个第一导电部分上依次形成导电柱和取向层; 在载体上形成密封剂，用于封装第一导电部分，导电柱和对准层; 在所述密封剂中的每个取向层上形成导电孔，并在所述导电通孔和所述密封剂上形成第二导电部分; 并移除载体。 每个第一导电部分和相应的导电柱，对准层和导电通孔形成导电结构。 取向层具有大于导电柱和导电通孔的垂直投影面积，从而减小导电柱和导电通孔的尺寸，从而增加布线密度和电子元件安装密度。

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