公开(公告)号：US06949961B2

公开(公告)日：2005-09-27

申请号：US10678769

申请日：2003-10-06

申请人： Stephen P. Robb ,  David K. Briggs

发明人： Stephen P. Robb ,  David K. Briggs

IPC分类号： H02H9/00 ,  H03K17/082 ,  H03K17/16 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H03K17/0822 ,  H02H9/004 ,  H03K17/167

摘要： In one embodiment, a power switch device (33) includes a first MOSFET device 41 and a second MOSFET device (42). A split gate structure (84) including a first gate electrode (48,87) controls the first MOSFET device (41). A second gate electrode (49,92) controls the second MOSFET device (42). A current limit device (38) is coupled to the first gate electrode (48,97) to turn on the first MOSFET device during a current limit mode. A comparator device (36) is coupled to the second gate electrode (49,92) to turn on the second MOSFET device (42) when the power switch device (33) is no longer in current limit mode.

摘要翻译： 在一个实施例中，功率开关器件（33）包括第一MOSFET器件41和第二MOSFET器件（42）。 包括第一栅极（48,87）的分离栅极结构（84）控制第一MOSFET器件（41）。 第二栅电极（49,92）控制第二MOSFET器件（42）。 电流限制装置（38）耦合到第一栅电极（48,97），以在电流限制模式期间导通第一MOSFET器件。 当电源开关装置（33）不再处于限流模式时，比较器装置（36）耦合到第二栅电极（49,92）以接通第二MOSFET装置（42）。

公开(公告)号：US07230299B2

公开(公告)日：2007-06-12

申请号：US11105222

申请日：2005-04-14

申请人： Stephen P. Robb ,  David K. Briggs

发明人： Stephen P. Robb ,  David K. Briggs

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/00

CPC分类号： H03K17/0822 ,  H02H9/004 ,  H03K17/167

摘要： In one embodiment, a power switch device (33) includes a first MOSFET device 41 and a second MOSFET device (42). A split gate structure (84) including a first gate electrode (48,87) controls the first MOSFET device (41). A second gate electrode (49,92) controls the second MOSFET device (42). A current limit device (38) is coupled to the first gate electrode (48,97) to turn on the first MOSFET device during a current limit mode. A comparator device (36) is coupled to the second gate electrode (49,92) to turn on the second MOSFET device (42) when the power switch device (33) is no longer in current limit mode.

摘要翻译： 在一个实施例中，功率开关器件（33）包括第一MOSFET器件41和第二MOSFET器件（42）。 包括第一栅极（48,87）的分离栅极结构（84）控制第一MOSFET器件（41）。 第二栅电极（49,92）控制第二MOSFET器件（42）。 电流限制装置（38）耦合到第一栅电极（48,97），以在电流限制模式期间导通第一MOSFET器件。 当电源开关装置（33）不再处于限流模式时，比较器装置（36）耦合到第二栅电极（49,92）以接通第二MOSFET装置（42）。

公开(公告)号：US07714381B2

公开(公告)日：2010-05-11

申请号：US11095135

申请日：2005-04-01

申请人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

发明人： Francine Y. Robb ,  Stephen P. Robb ,  Prasad Venkatraman ,  Zia Hossain

IPC分类号： H01L27/105

CPC分类号： H01L29/7813 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0878 ,  H01L29/66734

摘要： In one embodiment, a vertical power transistor is formed on a semiconductor substrate with other transistors. A portion of the semiconductor layer underlying the vertical power transistor is doped to provide a low on-resistance for the vertical power transistor.

摘要翻译： 在一个实施例中，在具有其它晶体管的半导体衬底上形成垂直功率晶体管。 垂直功率晶体管下面的半导体层的一部分被掺杂以为垂直功率晶体管提供低导通电阻。

公开(公告)号：US07537970B2

公开(公告)日：2009-05-26

申请号：US11367626

申请日：2006-03-06

申请人： Francine Y. Robb ,  Stephen P. Robb

发明人： Francine Y. Robb ,  Stephen P. Robb

IPC分类号： H01L21/332

CPC分类号： H03K17/063 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/0922 ,  H03K17/687 ,  H03K2217/0018

摘要： In one embodiment, a transistor is formed to have a first current flow path to selectively conduct current in both directions through the transistor and to have a second current flow path to selectively conduct current in one direction.

摘要翻译： 在一个实施例中，晶体管形成为具有第一电流流动路径，以选择性地在两个方向上导通电流通过晶体管，并且具有第二电流流动路径以选择性地在一个方向上导通电流。

公开(公告)号：US06841437B1

公开(公告)日：2005-01-11

申请号：US10464971

申请日：2003-06-20

申请人： Stephen P. Robb

发明人： Stephen P. Robb

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L21/823493 ,  H01L29/0847 ,  H01L29/66333 ,  H01L29/66712

摘要： A method of forming medium breakdown voltage vertical transistors (11) and lateral transistors (12, 13) on the same substrate (14) provides for optimizing the epitaxial layer (16) for the lateral transistors (12, 13). The vertical transistor (11) is formed in a well (18) that has a lower resistivity than the epitaxial layer (16) to provide the required low on-resistance for the vertical power transistor (11).

摘要翻译： 在同一衬底（14）上形成介质击穿电压垂直晶体管（11）和横向晶体管（12,13）的方法提供了优化用于横向晶体管（12,13）的外延层（16）。 垂直晶体管（11）形成在具有比外延层（16）更低的电阻率的阱（18）中，以为垂直功率晶体管（11）提供所需的低导通电阻。

公开(公告)号：US5536958A

公开(公告)日：1996-07-16

申请号：US433883

申请日：1995-05-02

申请人： Zheng Shen ,  Stephen P. Robb

发明人： Zheng Shen ,  Stephen P. Robb

IPC分类号： H01L29/866 ,  H01L27/02 ,  H01L27/04 ,  H01L29/06 ,  H01L29/78 ,  H01L23/62

CPC分类号： H01L29/7811 ,  H01L27/0255 ,  H01L29/0619 ,  H01L29/7806 ,  H01L29/7808 ,  H01L2924/0002

摘要： A semiconductor device is presented having an improved high voltage protection scheme that comprises an integrated Schottky diode (28) in conjunction with a plurality of back to back diodes (29) to limit a voltage potential that may arise between the gate (26) and drain terminals (27) of a semiconductor device. A second embodiment comprises a contact region (43) connected to a plurality of back to back diodes (46) configured so that some of the voltage is supported by the back to back diodes (46) and the remainder is supported by the substrate (39). These structures will support any excess voltage in the conduction mode, rather than the avalanche mode and may employ the use of a depletion region (51) to support a blocking voltage.

摘要翻译： 提出了具有改进的高电压保护方案的半导体器件，其包括与多个背对背二极管（29）结合的集成肖特基二极管（28），以限制可能在栅极（26）和漏极（26）之间产生的电压电位 端子（27）。 第二实施例包括连接到多个背对背二极管（46）的接触区域（43），其被配置成使得一些电压由背对背二极管（46）支撑，其余部分由衬底（39）支撑 ）。 这些结构将支持导通模式中的任何过电压而不是雪崩模式，并且可以使用耗尽区（51）来支持阻断电压。

公开(公告)号：US5365099A

公开(公告)日：1994-11-15

申请号：US202856

申请日：1994-02-25

申请人： John P. Phipps ,  Stephen P. Robb ,  Judy L. Sutor ,  Lewis E. Terry

发明人： John P. Phipps ,  Stephen P. Robb ,  Judy L. Sutor ,  Lewis E. Terry

IPC分类号： H01L29/866 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/861 ,  H03K17/08 ,  H03K17/16 ,  H01L29/10

CPC分类号： H01L29/7811 ,  H01L21/8221 ,  H01L27/0255 ,  H01L27/0688 ,  H01L29/7803 ,  H01L29/7808

摘要： A semiconductor device having an improved protection scheme and a temperature compensated sustaining voltage is provided by integrating a plurality of temperature compensated voltage reference diodes between the drain and the gate of the semiconductor device. The diodes protect the device by clamping the device's sustaining voltage to the total avalanche voltage of the diode. The device will dissipate any excessive energy in the conduction mode rather than in the more stressful avalanche mode. In addition, the plurality of diodes will provide for a temperature compensated sustaining voltage of the semiconductor device. The plurality of diodes are formed back-to-back in polysilicon. The positive temperature coefficient of the avalanching junction of each diode pair is compensated for by the negative temperature coefficient of the forward biased junction.

摘要翻译： 通过在半导体器件的漏极和栅极之间集成多个温度补偿电压参考二极管来提供具有改进的保护方案和温度补偿维持电压的半导体器件。 二极管通过将器件的维持电压钳位到二极管的总雪崩电压来保护器件。 该装置将在导通模式中消耗任何过多的能量，而不是在更紧张的雪崩模式下消耗。 此外，多个二极管将提供半导体器件的温度补偿维持电压。 在多晶硅中背对背地形成多个二极管。 每个二极管对的雪崩结的正温度系数由正向偏置结的负温度系数补偿。

公开(公告)号：US4970173A

公开(公告)日：1990-11-13

申请号：US489853

申请日：1990-03-02

申请人： Stephen P. Robb

发明人： Stephen P. Robb

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78

CPC分类号： H01L29/66712 ,  H01L29/1095 ,  H01L29/7802

摘要： A vertical field effect transistor having a first low resistivity region which determines breakdown voltage and a second low resistively region which is formed underneath a portion of a source is provided. The second low resistivity region lowers the gain of a parasitic bipolar transistor, and lowers resistance of a base region under the source of the field effect transistor, improving the commutating safe operating area of the vertical field effect transistor.

摘要翻译： 提供了具有确定击穿电压的第一低电阻率区域和形成在源的一部分下方的第二低电阻区域的垂直场效应晶体管。 第二低电阻率区域降低寄生双极晶体管的增益，并降低场效应晶体管源极下的基极区域的电阻，从而改善垂直场效应晶体管的整流安全工作面积。

公开(公告)号：US4924111A

公开(公告)日：1990-05-08

申请号：US263746

申请日：1988-10-31

申请人： Floyd E. Anderson ,  Stephen P. Robb

发明人： Floyd E. Anderson ,  Stephen P. Robb

IPC分类号： H01L27/02 ,  H03K17/14

CPC分类号： H03K17/145 ,  H01L27/0211 ,  Y10S257/92

摘要： An integrated circuit having a microprocessor core interfaced to large power transistors is described. This integrated circuit provides the capability to intelligently control and drive loads requiring currents exceeding 250 milli amps. The large power transistors are built in a technology compatible with the microprocessor core technology resulting in a more readily manufacturable circuit. The microprocessor core is layed out in a manner which provides the greatest distance between the most heat sensitive microprocessor core circuits and the power devices. On chip temperature sensing and feedback is provided for junction temperature monitoring and control.

摘要翻译： 描述了具有与大功率晶体管连接的微处理器核心的集成电路。 该集成电路提供智能控制和驱动需要电流超过250毫安的负载的能力。 大功率晶体管内置于与微处理器核心技术相兼容的技术，从而形成更容易制造的电路。 微处理器内核以最热敏微处理器核心电路和功率器件之间提供最大距离的方式布置。 提供片上温度检测和反馈，用于结温监测和控制。

公开(公告)号：US4775879A

公开(公告)日：1988-10-04

申请号：US027366

申请日：1987-03-18

申请人： Stephen P. Robb ,  Lewis E. Terry

发明人： Stephen P. Robb ,  Lewis E. Terry

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L29/7802 ,  H01L29/0696

摘要： A vertical field effect transistor is provided which has its sources arranged in a pattern to essentially eliminate inactive common drain area between the sources. The preferred arrangement is to use rectangular source areas to form columns and rows in the arrangement. Every other row is shifted so that a source in a shifted row is positioned between sources in an adjacent row. The rows are then spaced closer together thereby achieving the substantial elimination of inactive drain area. The elimination of inactive drain area results in low on resistance during the conductive state of the vertical field effect transistor.