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    Interposer structures and methods of manufacturing the same
    1.
    发明授权
    Interposer structures and methods of manufacturing the same 失效
    插件结构及其制造方法

    公开(公告)号：US07688095B2

    公开(公告)日：2010-03-30

    申请号：US11741345

    申请日：2007-04-27

    申请人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

    发明人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4038

    摘要： Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 μm.

    摘要翻译： 描述了用于半导体工业的柔性和刚性插入件及其制造方法。 自动催化过程用于最小化与柔性插入物的生产相关的成本，同时提高产量和寿命。 电接触区域容易隔离，并且由于插入器的所有部分一次镀覆，因此腐蚀的风险降低。 从插入件的柔性部分突出的引线可容纳更多种待测试的部件。 刚性插入件包括从固定到基板的探针垫突出的销。 针的刚度穿过待测接触垫上的氧化物。 易于使用的半导体材料和工艺用于制造根据本发明的柔性和刚性插入件。 柔性和刚性插入件可以容纳低至25μm的间距。

    INTERPOSER STRUCTURES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    INTERPOSER STRUCTURES AND METHODS OF MANUFACTURING THE SAME 有权
    中间件结构及其制造方法

    公开(公告)号：US20100038126A1

    公开(公告)日：2010-02-18

    申请号：US12542935

    申请日：2009-08-18

    申请人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

    发明人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

    IPC分类号： H05K1/11

    CPC分类号： G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4038

    摘要： Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 μm.

    摘要翻译： 描述了用于半导体工业的柔性和刚性插入件及其制造方法。 自动催化过程用于最小化与柔性插入物的生产相关的成本，同时提高产量和寿命。 电接触区域容易隔离，并且由于插入器的所有部分一次镀覆，因此腐蚀的风险降低。 从插入件的柔性部分突出的引线可容纳更多种待测试的部件。 刚性插入件包括从固定到基板的探针垫突出的销。 针的刚度穿过待测接触垫上的氧化物。 易于使用的半导体材料和工艺用于制造根据本发明的柔性和刚性插入件。 柔性和刚性插入件可以容纳低至25μm的间距。

    Interposer structures and methods of manufacturing the same
    3.
    发明授权
    Interposer structures and methods of manufacturing the same 有权
    插件结构及其制造方法

    公开(公告)号：US08159248B2

    公开(公告)日：2012-04-17

    申请号：US12542935

    申请日：2009-08-18

    申请人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

    发明人： Steven A. Cordes ,  Matthew J. Farinelli ,  Sherif A. Goma

    IPC分类号： G01R31/00

    CPC分类号： G01R1/0735 ,  G01R3/00 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4038

    摘要： Flexible and rigid interposers for use in the semiconductor industry and methods for manufacturing the same are described. Auto-catalytic processes are used to minimize the costs associated with the production of flexible interposers, while increasing the yield and lifetime. Electrical contact regions are easily isolated and the risk of corrosion is reduced because all portions of the interposer are plated at once. Leads projecting from the flexible portion of the interposers accommodate a greater variety of components to be tested. Rigid interposers include a pin projecting from a probe pad affixed to a substrate. The rigidity of the pin penetrates oxides on a contact pad to be tested. Readily available semiconductor materials and processes are used to manufacture the flexible and rigid interposers according to the invention. The flexible and rigid interposers can accommodate pitches down to 25 μm.

    摘要翻译： 描述了用于半导体工业的柔性和刚性插入件及其制造方法。 自动催化过程用于最小化与柔性插入物的生产相关的成本，同时提高产量和寿命。 电接触区域容易隔离，并且由于插入器的所有部分一次镀覆，因此腐蚀的风险降低。 从插入件的柔性部分突出的引线可容纳更多种待测试的部件。 刚性插入件包括从固定到基板的探针垫突出的销。 针的刚度穿过待测接触垫上的氧化物。 易于使用的半导体材料和工艺用于制造根据本发明的柔性和刚性插入件。 柔性和刚性插入件可以容纳低至25μm的间距。

    PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY
    8.
    发明申请
    PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY 失效
    处理极端地形图

    公开(公告)号：US20110130005A1

    公开(公告)日：2011-06-02

    申请号：US13024711

    申请日：2011-02-10

    申请人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

    发明人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

    IPC分类号： H01L21/3105

    CPC分类号： H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

    摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

    摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。

    PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY
    9.
    发明申请
    PROCESSING FOR OVERCOMING EXTREME TOPOGRAPHY 有权
    处理极端地形图

    公开(公告)号：US20090298292A1

    公开(公告)日：2009-12-03

    申请号：US12538515

    申请日：2009-08-10

    申请人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

    发明人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

    IPC分类号： H01L21/3105

    CPC分类号： H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

    摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

    摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。

    Processing for overcoming extreme topography
    10.
    发明授权
    Processing for overcoming extreme topography 有权
    克服极端地形的处理

    公开(公告)号：US07915064B2

    公开(公告)日：2011-03-29

    申请号：US12538515

    申请日：2009-08-10

    申请人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

    发明人： Guy A. Cohen ,  Steven A. Cordes ,  Sherif A. Goma ,  Joanna Rosner ,  Jeannine M. Trewhella

    IPC分类号： H01L21/00 ,  H01L21/311

    CPC分类号： H01L21/31051 ,  B81C1/00611 ,  B81C2201/0119 ,  H01L21/0272 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/3212 ,  H01L21/76838

    摘要： A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.

    摘要翻译： 通过首先平面化半导体衬底中的空腔以便创建用于后续光刻处理的平坦表面来克服极端形貌的过程。 作为极端形貌的平面化处理的结果，可以进行随后的光刻处理，包括紧邻极端地形表面（例如，深空腔或通道）的特征沉积，并且包括在空腔内沉积特征。 在第一实施例中，用于平面化半导体衬底中的腔的方法包括施加具有高耐化学性的干膜抗蚀剂。 在第二实施例中，用于平坦化空腔的方法包括使用诸如聚合物，玻璃旋转和冶金的材料来填充空腔。