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公开(公告)号：US09343389B2
公开(公告)日：2016-05-17
申请号：US14827056
申请日：2015-08-14
申请人： INTEL CORPORATION
IPC分类号： H01L23/32 , H01L23/498 , H01L25/065 , H01L25/00 , H01L23/00
CPC分类号： H01L25/0657 , H01F7/04 , H01L23/32 , H01L23/49811 , H01L23/49866 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/10135 , H01L2224/10165 , H01L2224/11332 , H01L2224/11522 , H01L2224/132 , H01L2224/13298 , H01L2224/13355 , H01L2224/13357 , H01L2224/1336 , H01L2224/13444 , H01L2224/13464 , H01L2224/13469 , H01L2224/1601 , H01L2224/16225 , H01L2224/16227 , H01L2224/811 , H01L2224/81139 , H01L2224/8114 , H01L2224/81193 , H01L2225/06513 , H01L2225/06527 , H01L2225/06531 , H01L2225/06568 , H01L2225/06593 , H01L2225/06596 , H01L2924/014 , H01L2924/00014 , H01L2924/207 , H01L2924/00012
摘要： Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.
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公开(公告)号：US09299686B1
公开(公告)日：2016-03-29
申请号：US14598352
申请日：2015-01-16
IPC分类号： H01L23/48 , H01L25/065 , H01L23/522 , H01L23/528 , H01L23/532 , H01L23/473 , H01L25/00 , H01L21/768 , H01L21/48
CPC分类号： H01L21/4882 , H01L21/76802 , H01L21/76876 , H01L23/147 , H01L23/15 , H01L23/3677 , H01L23/473 , H01L23/49827 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/11003 , H01L2224/111 , H01L2224/1112 , H01L2224/13011 , H01L2224/13017 , H01L2224/13018 , H01L2224/13147 , H01L2224/13566 , H01L2224/13578 , H01L2224/136 , H01L2224/13611 , H01L2224/13624 , H01L2224/1601 , H01L2224/16146 , H01L2224/16227 , H01L2224/16505 , H01L2224/811 , H01L2224/81815 , H01L2224/8192 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06589 , H01L2924/01029 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/01047
摘要： A method and structures are provided for implementing individual integrated circuit chip attach in a three dimensional (3D) stack. A plurality of hollow copper pillars is formed, and the hollow copper pillars are coated with lead free solder using vapor deposition.
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公开(公告)号：US20150357311A1
公开(公告)日：2015-12-10
申请号：US14827056
申请日：2015-08-14
申请人： INTEL CORPORATION
IPC分类号： H01L25/065
CPC分类号： H01L25/0657 , H01F7/04 , H01L23/32 , H01L23/49811 , H01L23/49866 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/50 , H01L2224/10135 , H01L2224/10165 , H01L2224/11332 , H01L2224/11522 , H01L2224/132 , H01L2224/13298 , H01L2224/13355 , H01L2224/13357 , H01L2224/1336 , H01L2224/13444 , H01L2224/13464 , H01L2224/13469 , H01L2224/1601 , H01L2224/16225 , H01L2224/16227 , H01L2224/811 , H01L2224/81139 , H01L2224/8114 , H01L2224/81193 , H01L2225/06513 , H01L2225/06527 , H01L2225/06531 , H01L2225/06568 , H01L2225/06593 , H01L2225/06596 , H01L2924/014 , H01L2924/00014 , H01L2924/207 , H01L2924/00012
摘要： Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication methods and systems incorporating such magnetic contacts. A first IC substrate may have a first magnet coupled with a first electrical routing feature. A second IC substrate may have a second magnet coupled with a second electrical routing feature. The magnets may be embedded in the IC substrates and/or electrical routing features. The magnets may generate a magnetic field that extends across a gap between the first and second electrical routing features. Electrically conductive magnetic particles may be applied to one or both of the IC substrates to form a magnetic interconnect structure that extends across the gap. In some embodiments, magnetic contacts may be demagnetized by heating the magnets to a corresponding partial demagnetization temperature (PDT) or Curie temperature. Other embodiments may be described and/or claimed.
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4.发明申请公开(公告)号：US20150311188A1
公开(公告)日：2015-10-29
申请号：US14694868
申请日：2015-04-23
发明人： Jianhong MAO , Fengqin HAN , Zhiwei WANG , Wenfen CHANG
CPC分类号： H01L25/50 , H01L21/561 , H01L21/565 , H01L21/568 , H01L22/14 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L24/96 , H01L24/97 , H01L25/0657 , H01L2224/0392 , H01L2224/0401 , H01L2224/0557 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/16147 , H01L2224/2919 , H01L2224/32145 , H01L2224/73204 , H01L2224/81002 , H01L2224/811 , H01L2224/83121 , H01L2224/83855 , H01L2224/83862 , H01L2224/83868 , H01L2224/83871 , H01L2224/83874 , H01L2224/92 , H01L2224/92143 , H01L2224/94 , H01L2224/96 , H01L2224/97 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/00012 , H01L2924/01015 , H01L2924/01005 , H01L2224/81 , H01L2224/83 , H01L2224/03 , H01L21/56 , H01L21/78 , H01L21/304
摘要： The present invention provides a method of fabricating a 3D stacked IC SiP which includes: providing a first semiconductor wafer having a plurality of first dies formed thereon, each having a first wire bond pad and a first dielectric layer, at least a portion of the first wire bond pad is not covered by the first dielectric layer and constitutes an exposed area of the first die; providing a plurality of second dies, each having a second wire bond pad and a second dielectric layer, at least a portion of the second wire bond pad is not covered by the second dielectric layer and constitutes an exposed area of the second die different in size from that of the first die; aligning the second dies with the first dies and bonding the second dielectric layer to the first dielectric layer; plating the first semiconductor wafer bonded with the second dies.
摘要翻译： 本发明提供了一种制造3D堆叠IC SiP的方法，其包括：提供第一半导体晶片，其具有形成在其上的多个第一裸片，每个具有第一引线键合焊盘和第一介电层，第一半导体晶片的至少一部分 引线接合焊盘不被第一介电层覆盖并构成第一裸片的暴露区域; 提供多个第二管芯，每个第二管芯具有第二引线接合焊盘和第二介电层，第二引线接合焊盘的至少一部分不被第二介电层覆盖，并且构成尺寸不同的第二裸片的暴露区域 从第一个死亡的; 将所述第二管芯与所述第一管芯对准并且将所述第二介电层接合到所述第一介电层; 电镀与第二模具结合的第一半导体晶片。
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公开(公告)号：US09117772B2
公开(公告)日：2015-08-25
申请号：US13527422
申请日：2012-06-19
申请人： Zheng-Yi Lim , Yi-Wen Wu , Tzong-Hann Yang , Ming-Che Ho , Chung-Shi Liu
发明人： Zheng-Yi Lim , Yi-Wen Wu , Tzong-Hann Yang , Ming-Che Ho , Chung-Shi Liu
IPC分类号： H01L21/44 , H01L23/31 , H01L25/10 , H01L25/00 , H01L25/065 , H01L21/56 , H01L23/498 , H01L23/00
CPC分类号： H01L24/81 , H01L21/56 , H01L23/3107 , H01L23/3128 , H01L23/49811 , H01L23/49816 , H01L23/49833 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/13016 , H01L2224/13017 , H01L2224/13018 , H01L2224/13023 , H01L2224/13124 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13582 , H01L2224/13583 , H01L2224/13611 , H01L2224/13644 , H01L2224/13647 , H01L2224/13655 , H01L2224/13657 , H01L2224/13664 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/16501 , H01L2224/16505 , H01L2224/32135 , H01L2224/32141 , H01L2224/32145 , H01L2224/81085 , H01L2224/811 , H01L2224/8112 , H01L2224/81121 , H01L2224/81193 , H01L2224/81232 , H01L2224/81355 , H01L2224/81359 , H01L2224/81801 , H01L2224/8192 , H01L2225/06513 , H01L2225/06517 , H01L2225/0652 , H01L2225/1023 , H01L2225/1058 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/15311 , H01L2924/1533 , H01L2924/15331 , H01L2924/181 , H01L2924/1815 , H01L2924/18161 , H01L2924/3841 , H01L2924/00014 , H01L2924/00012 , H01L2924/01005 , H01L2924/01074 , H01L2924/01015 , H01L2924/06 , H01L2924/00
摘要： A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector.
摘要翻译： 一种方法包括将第一包装部件的第一电连接器与第二包装部件的第二电连接器对准。 利用第一电连接器与第二电连接器对准，金属层被电镀在第一和第二电连接器上。 金属层将第一电连接器连接到第二电连接器。
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公开(公告)号：US20150228617A1
公开(公告)日：2015-08-13
申请号：US14338050
申请日：2014-07-22
发明人： Haksun LEE , KWANG-SEONG CHOI , Yong Sung EOM , Hyun-cheol BAE
IPC分类号： H01L23/00
CPC分类号： H01L24/83 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/81 , H01L2224/0401 , H01L2224/05568 , H01L2224/16238 , H01L2224/2929 , H01L2224/293 , H01L2224/32225 , H01L2224/32501 , H01L2224/32505 , H01L2224/73204 , H01L2224/81002 , H01L2224/811 , H01L2224/83224 , H01L2224/83851 , H01L2224/83859 , H01L2224/83886 , H01L2224/83948 , H01L2224/83986 , H01L2224/92125 , H01L2924/00014 , H01L2924/12042 , H01L2924/00 , H01L2924/014
摘要： Provided is a semiconductor device and a method of manufacturing the same. In the method of manufacturing a semiconductor device, a substrate is prepared which is transparent and has a plurality of first electrodes thereon, and a semiconductor chip having a plurality of second electrodes thereon is disposed on the substrate to allow the first and second electrodes to respectively face each other. A polymer layer including solder particles and an oxidizing agent is formed between the substrate and the semiconductor chip, and the solder particles is locally fused between the first and second electrodes by using a laser beam and a fused solder layer is formed which electrically connects between the first and second electrodes.
摘要翻译： 提供一种半导体器件及其制造方法。 在制造半导体器件的方法中，准备透明的衬底并且在其上具有多个第一电极，并且其上具有多个第二电极的半导体芯片设置在衬底上以允许第一和第二电极分别 面对面 在衬底和半导体芯片之间形成包括焊料颗粒和氧化剂的聚合物层，并且通过使用激光束将焊料颗粒局部融合在第一和第二电极之间，并且形成熔融焊料层， 第一和第二电极。
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公开(公告)号：US20150214166A1
公开(公告)日：2015-07-30
申请号：US14685136
申请日：2015-04-13
发明人： Kai-Ming Ching
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L23/5283 , H01L24/03 , H01L24/10 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02126 , H01L2224/0361 , H01L2224/03622 , H01L2224/0401 , H01L2224/05557 , H01L2224/05558 , H01L2224/05572 , H01L2224/05644 , H01L2224/13 , H01L2224/13009 , H01L2224/131 , H01L2224/13147 , H01L2224/13582 , H01L2224/13644 , H01L2224/13655 , H01L2224/16059 , H01L2224/16147 , H01L2224/811 , H01L2224/81139 , H01L2224/8114 , H01L2224/81815 , H01L2225/06513 , H01L2225/06555 , H01L2225/06593 , H01L2924/00014 , H01L2924/0002 , H01L2924/01002 , H01L2924/01006 , H01L2924/01015 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/01014 , H01L2924/00 , H01L2224/05552
摘要： A method and system of stacking and aligning a plurality of integrated circuits. The method includes the steps of providing a first integrated circuit having at least one funnel-shaped socket, providing a second integrated circuit, aligning at least one protrusion on the second integrated circuit with the at least one funnel-shaped socket, and bonding the first integrated circuit to the second integrated circuit. The system includes a first integrated circuit having at least one funnel-shaped socket, a metallization-diffusion barrier disposed on the interior of the funnel-shaped socket, and a second integrated circuit. The at least one funnel-shaped socket is adapted to receive a portion of the second integrated circuit.
摘要翻译： 堆叠和对准多个集成电路的方法和系统。 该方法包括以下步骤：提供具有至少一个漏斗形插座的第一集成电路，提供第二集成电路，将第二集成电路上的至少一个突起与至少一个漏斗形插座对准，并将第一集成电路 集成电路到第二集成电路。 该系统包括具有至少一个漏斗形插座，设置在漏斗形插座内部的金属化扩散屏障和第二集成电路的第一集成电路。 所述至少一个漏斗形插座适于接收第二集成电路的一部分。
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公开(公告)号：US20140376200A1
公开(公告)日：2014-12-25
申请号：US13924002
申请日：2013-06-21
申请人： Invensas Corporation
CPC分类号： H01L24/13 , H01L21/563 , H01L23/564 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/50 , H01L2224/02372 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05147 , H01L2224/05155 , H01L2224/05557 , H01L2224/05568 , H01L2224/05571 , H01L2224/05609 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05664 , H01L2224/10145 , H01L2224/1146 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/11903 , H01L2224/13024 , H01L2224/13025 , H01L2224/13109 , H01L2224/13111 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13157 , H01L2224/13164 , H01L2224/1319 , H01L2224/14517 , H01L2224/1601 , H01L2224/16057 , H01L2224/16058 , H01L2224/16104 , H01L2224/16105 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16503 , H01L2224/17505 , H01L2224/17517 , H01L2224/32145 , H01L2224/32225 , H01L2224/73204 , H01L2224/81001 , H01L2224/81007 , H01L2224/811 , H01L2224/81139 , H01L2224/8192 , H01L2224/83104 , H01L2224/9201 , H01L2224/9212 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2924/00014 , H05K1/181 , H05K3/30 , Y10T29/4913 , H01L2924/00012 , H01L2924/01015 , H01L2924/01074 , H01L2224/05552
摘要： Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.
摘要翻译： 本文公开了微电子组件及其制造方法。 在一个实施例中，形成微电子组件的方法包括组装第一和第二部件以使第一和第二部件的第一主表面彼此面对并且彼此隔开预定间隔，第一部件具有第一和第二相对 主表面，在第一和第二主表面之间沿第一方向延伸的第一厚度和在第一主表面处的多个第一金属连接元件，第二部件在第一主要部分具有多个第二金属连接元件 第二部件的表面; 以及电镀多个金属连接器区域，每个金属连接器区域在第一方向上在相应的第一连接元件和与相应的第一连接元件相对的相应的第二连接元件之间连续延伸。
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公开(公告)号：US08742595B1
公开(公告)日：2014-06-03
申请号：US13953238
申请日：2013-07-29
发明人： Bruce C. S. Chou
CPC分类号： B81B3/0018 , B81B2203/0307 , B81B2203/04 , B81B2207/07 , B81C1/00476 , B81C1/00801 , B81C2201/0109 , H01L24/13 , H01L24/80 , H01L24/81 , H01L24/92 , H01L2224/13009 , H01L2224/13138 , H01L2224/80011 , H01L2224/80012 , H01L2224/80013 , H01L2224/80031 , H01L2224/80047 , H01L2224/8009 , H01L2224/80092 , H01L2224/80931 , H01L2224/81002 , H01L2224/81007 , H01L2224/811 , H01L2224/9202 , H01L2924/1461 , H01L21/76898 , H01L2924/01014 , H01L2924/00
摘要： The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.
摘要翻译： 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。
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公开(公告)号：US20130020718A1
公开(公告)日：2013-01-24
申请号：US13189057
申请日：2011-07-22
申请人： Bruce C.S. Chou
发明人： Bruce C.S. Chou
CPC分类号： B81B3/0018 , B81B2203/0307 , B81B2203/04 , B81B2207/07 , B81C1/00476 , B81C1/00801 , B81C2201/0109 , H01L24/13 , H01L24/80 , H01L24/81 , H01L24/92 , H01L2224/13009 , H01L2224/13138 , H01L2224/80011 , H01L2224/80012 , H01L2224/80013 , H01L2224/80031 , H01L2224/80047 , H01L2224/8009 , H01L2224/80092 , H01L2224/80931 , H01L2224/81002 , H01L2224/81007 , H01L2224/811 , H01L2224/9202 , H01L2924/1461 , H01L21/76898 , H01L2924/01014 , H01L2924/00
摘要： The present invention provides a MEMS structure comprising confined sacrificial oxide layer and a bonded Si layer. Polysilicon stack is used to fill aligned oxide openings and MEMS vias on the sacrificial layer and the bonded Si layer respectively. To increase the design flexibility, some conductive polysilicon layer can be further deployed underneath the bonded Si layer to form the functional sensing electrodes or wiring interconnects. The MEMS structure can be further bonded to a metallic layer on top of the Si layer and the polysilicon stack.
摘要翻译： 本发明提供一种MEMS结构，其包括受限的牺牲氧化物层和结合的Si层。 多晶硅叠层用于在牺牲层和结合的Si层上分别填充对准的氧化物开口和MEMS通孔。 为了增加设计灵活性，可以将一些导电多晶硅层进一步布置在结合的Si层下面以形成功能感测电极或布线互连。 MEMS结构可以进一步结合到Si层和多晶硅叠层顶部的金属层。
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