公开(公告)号：US07485562B2

公开(公告)日：2009-02-03

申请号：US11028374

申请日：2005-01-03

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up, wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

摘要翻译： 本发明定义了在芯片解决方案上提供多芯片多层系统的封装实现。 实现了包含在形成在单独基板中的空腔内的多个和多种已知的良好模具的更大整合。 在多芯片配置之上的附加再分布和互连层可以形成为具有终止于诸如导电凸块或球的电连接的再分布层。 在一个实施例中，衬底空腔以倒装芯片配置接收多个半导体晶片的信号器件连接，例如导电凸块。 然后将衬底的背面的一部分去除足以露出导电凸块的深度。 在另一个实施例中，空腔容纳半导体晶片，其有源表面朝上，其中形成金属层连接并耦合到半导体晶片的接合焊盘或其它电连接器。 还公开了包含包装的计算系统。

公开(公告)号：US07274094B2

公开(公告)日：2007-09-25

申请号：US10233319

申请日：2002-08-28

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

IPC分类号： H01L23/495

CPC分类号： H01L31/0203 ,  H01L2224/16245

摘要： A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.

摘要翻译： 无引线图像传感器封装及其组装方法。 在第一实施例中，图像传感器芯片以倒装芯片方式安装在封装外壳的底侧空腔内，使得图像传感器芯片上的感测电路通过封装壳体的顶侧中的孔露出。 透明的密封剂材料沉积在孔内以包围封装外壳和图像传感器芯片之间的互连结。 透明盖通过密封剂材料保持在孔的适当位置。 图像传感器芯片的背面被暴露。 在特别适用于高端图像传感器的第二实施例中，不需要密封材料。 相反，背盖被密封到封装壳体中的凸缘表面以覆盖底侧空腔。 形成在背盖上的压缩构件与图像传感器芯片接触并保持互连接合完整性。

公开(公告)号：US07193312B2

公开(公告)日：2007-03-20

申请号：US11222365

申请日：2005-09-07

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Siu Waf Low ,  Meow Koon Eng ,  Swee Kwang Chua ,  Shuang Wu Huang ,  Yong Loo Neo ,  Wei Zhou

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Siu Waf Low ,  Meow Koon Eng ,  Swee Kwang Chua ,  Shuang Wu Huang ,  Yong Loo Neo ,  Wei Zhou

IPC分类号： H01L23/48

CPC分类号： H01L25/50 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

摘要： Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

公开(公告)号：US06964881B2

公开(公告)日：2005-11-15

申请号：US10229914

申请日：2002-08-27

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC分类号： H01L21/60 ,  H01L23/498 ,  H01L23/538 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die are contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the cavities of the substrate receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the back surface of the substrate is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with the active surface of the semiconductor dice facing up, wherein metal layer connections are formed and coupled bond pads or other electrical connectors of the semiconductor dice.

摘要翻译： 本发明定义了在芯片解决方案上提供多芯片多层系统的封装实现。 实现了包含在形成在单独基板中的空腔内的多个和多种已知的良好模具的更大整合。 在多芯片配置之上的附加再分布和互连层可以形成为具有终止于诸如导电凸块或球的电连接的再分布层。 在一个实施例中，衬底的空腔以倒装芯片配置接收多个半导体晶片的信号器件连接，例如导电凸块。 然后将衬底背面的一部分去除足以露出导电凸块的深度。 在另一个实施例中，空腔接收半导体晶片，其中半导体晶片的有源表面朝上，其中形成金属层连接并耦合到半导体晶片的接合焊盘或其它电连接器。

公开(公告)号：US07112471B2

公开(公告)日：2006-09-26

申请号：US10693376

申请日：2003-10-23

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Yong Loo Neo ,  Swee Kwang Chua ,  Siu Waf Low

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L31/0203 ,  H01L2224/16245

摘要： A leadless image sensor package and methods for its assembly. In a first embodiment, an image sensor chip is mounted within a bottom-side cavity of a package shell in a flip-chip manner such that sensing circuitry on the image sensor chip is exposed through an aperture in the top side of the package shell. A transparent encapsulant material is deposited within the aperture to encase interconnect bonds between the package shell and the image sensor chip. A transparent lid is held in place over the aperture by the encapsulant material. The back surface of the image sensor chip is left exposed. In a second embodiment particularly suitable for high-end image sensors, an encapsulant material is not required. Instead, a backing cap is hermetically sealed to a ledge surface in the package shell to cover the bottom-side cavity. A compression member formed on the backing cap contacts the image sensor chip and maintains interconnect bond integrity.

摘要翻译： 无引线图像传感器封装及其组装方法。 在第一实施例中，图像传感器芯片以倒装芯片方式安装在封装外壳的底侧空腔内，使得图像传感器芯片上的感测电路通过封装壳体的顶侧中的孔露出。 透明的密封剂材料沉积在孔内以包围封装外壳和图像传感器芯片之间的互连结。 透明盖通过密封剂材料保持在孔的适当位置。 图像传感器芯片的背面被暴露。 在特别适用于高端图像传感器的第二实施例中，不需要密封材料。 相反，背盖被密封到封装壳体中的凸缘表面以覆盖底侧空腔。 形成在背盖上的压缩构件与图像传感器芯片接触并保持互连接合完整性。

公开(公告)号：US06825553B2

公开(公告)日：2004-11-30

申请号：US10656352

申请日：2003-09-05

申请人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

发明人： Swee Kwang Chua ,  Siu Waf Low ,  Yong Poo Chia ,  Meow Koon Eng ,  Yong Loo Neo ,  Suan Jeung Boon ,  Suangwu Huang ,  Wei Zhou

IPC分类号： H01L2352

CPC分类号： H01L23/5389 ,  H01L21/568 ,  H01L23/49816 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2224/05599

摘要： The present invention defines a packaging implementation providing a multichip multilayer system on a chip solution. Greater integration of a plurality and variety of known good die contained within cavities formed in a separate substrate is achieved. Additional redistribution and interconnect layers above the multichip configuration may be formed with the redistribution layers terminating in electrical connections such as conductive bumps or balls. In one embodiment, the substrate cavities receive signal device connections, such as conductive bumps, of a plurality of semiconductor dice in a flip-chip configuration. A portion of the substrate's back surface is then removed to a depth sufficient to expose the conductive bumps. In another embodiment, the cavities receive the semiconductor dice with their active surface facing up wherein metal layer connections are formed and coupled to bond pads or other electrical connectors of the semiconductor dice. Computing systems incorporating the packaging are also disclosed.

公开(公告)号：US07553697B2

公开(公告)日：2009-06-30

申请号：US11595067

申请日：2006-11-09

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

IPC分类号： H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/24226 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device package and method of fabricating the same are disclosed. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

摘要翻译： 公开了一种半导体器件封装及其制造方法。 半导体器件封装可以包括各种半导体管芯，从而提供芯片上的系统解决方案。 半导体裸片连接到与导电迹线层相关联的连接位置，例如通过倒装芯片技术。 多个电路连接元件也直接地或通过附加的中间导电迹线层耦合到导电迹线层。 可以在骰子和衬底之上形成封装层。 电路连接元件的一部分通过封装层保持暴露，以连接到外部设备。 可以形成多个导电凸块，每个导电凸块设置在电路连接元件的暴露部分的顶部，以便于与外部装置的电连接。

公开(公告)号：US07304375B2

公开(公告)日：2007-12-04

申请号：US11222462

申请日：2005-09-07

申请人： Suan Jeung Boon ,  Yong Poo Chia ,  Siu Waf Low ,  Meow Koon Eng ,  Swee Kwang Chua ,  Shuang Wu Huang ,  Yong Loo Neo ,  Wei Zhou

发明人： Suan Jeung Boon ,  Yong Poo Chia ,  Siu Waf Low ,  Meow Koon Eng ,  Swee Kwang Chua ,  Shuang Wu Huang ,  Yong Loo Neo ,  Wei Zhou

IPC分类号： H01L23/02

CPC分类号： H01L25/50 ,  H01L23/3114 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/24 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/73267 ,  H01L2224/85399 ,  H01L2225/06551 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

摘要： Systems and methods for packaging integrated circuit chips in castellation wafer level packaging are provided. The active circuit areas of the chips are coupled to castellation blocks and, depending on the embodiment, input/output pads. The castellation blocks and input/output pads are encapsulated and held in place by an encapsulant. When the devices are being fabricated, the castellation blocks and input/output pads are sawed through. If necessary, the wafer portion on which the devices are fabricated may be thinned. The packages may be used as a leadless chip carrier package or may be stacked on top of one another. When stacked, the respective contacts of the packages are preferably coupled. Data may be written to, and received from, packaged chips when a chip is activated. Chips may be activated by applying the appropriate signal or signals to the appropriate contact or contacts.

摘要翻译： 提供了用于封装晶圆级封装中集成电路芯片的系统和方法。 芯片的有源电路区域耦合到城堡块，并且根据实施例，输入/输出焊盘。 城堡块和输入/输出垫通过密封剂封装并保持就位。 当制造设备时，将城堡块和输入/输出垫片穿过。 如果需要，可以使其上制造器件的晶片部分变薄。 封装可以用作无引线芯片载体封装，或者可以堆叠在彼此之上。 当堆叠时，封装的相应触点优选地联接。 当芯片被激活时，可以将数据写入和从芯片接收。 可以通过将适当的信号或信号施加到适当的触点或触点来激活芯片。

公开(公告)号：US07173330B2

公开(公告)日：2007-02-06

申请号：US11171124

申请日：2005-06-30

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

IPC分类号： H01L23/12 ,  H01L23/053

CPC分类号： H01L25/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/24226 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

公开(公告)号：US06987031B2

公开(公告)日：2006-01-17

申请号：US10229908

申请日：2002-08-27

申请人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

发明人： Meow Koon Eng ,  Yong Poo Chia ,  Yong Loo Neo ,  Suan Jeung Boon ,  Siu Waf Low ,  Swee Kwang Chua ,  Suangwu Huang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/4857 ,  H01L23/3128 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/24226 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83851 ,  H01L2224/90 ,  H01L2924/00011 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2224/29075 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device package and method of fabricating the same. The semiconductor device package may include a variety of semiconductor dice, thereby providing a system on a chip solution. The semiconductor dice are attached to connection locations associated with a conductive trace layer such as through flip-chip technology. A plurality of circuit connection elements is also coupled to the conductive trace layer, either directly or through additional, intervening conductive trace layers. An encapsulation layer may be formed over the dice and substrate. Portions of the circuit connection elements remain exposed through the encapsulation layer for connection to external devices. A plurality of conductive bumps may be formed, each conductive bump being disposed atop an exposed portion of a circuit connection element, to facilitate electrical connection with an external device.

摘要翻译： 一种半导体器件封装及其制造方法。 半导体器件封装可以包括各种半导体管芯，从而提供芯片上的系统解决方案。 半导体裸片连接到与导电迹线层相关联的连接位置，例如通过倒装芯片技术。 多个电路连接元件也直接地或通过附加的中间导电迹线层耦合到导电迹线层。 可以在骰子和衬底之上形成封装层。 电路连接元件的一部分通过封装层保持暴露，以连接到外部设备。 可以形成多个导电凸块，每个导电凸块设置在电路连接元件的暴露部分的顶部，以便于与外部装置的电连接。