公开(公告)号：US09961784B2

公开(公告)日：2018-05-01

申请号：US15475134

申请日：2017-03-31

Applicant: Subtron Technology Co., Ltd.

Inventor： Tzu-Wei Huang

IPC: H05K3/46 ,  H05K3/42 ,  H05K3/00 ,  H05K3/02 ,  H05K1/11 ,  B23K11/11 ,  B32B37/02 ,  B32B37/04 ,  B32B38/10 ,  B32B38/04 ,  B32B37/00 ,  B23K101/42

CPC classification number: H05K3/4682 ,  B23K11/11 ,  B23K2101/42 ,  B32B37/0084 ,  B32B37/02 ,  B32B37/04 ,  B32B38/04 ,  B32B38/10 ,  B32B2038/047 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/00 ,  B32B2311/12 ,  B32B2457/00 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1536 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.

公开(公告)号：US20170208696A1

公开(公告)日：2017-07-20

申请号：US15475134

申请日：2017-03-31

Applicant: Subtron Technology Co., Ltd.

Inventor： Tzu-Wei Huang

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/02 ,  H05K1/11 ,  B32B38/10 ,  B32B37/02 ,  B32B37/04 ,  B32B37/00 ,  B32B38/04 ,  H05K3/42 ,  B23K11/11

CPC classification number: H05K3/4682 ,  B23K11/11 ,  B23K2101/42 ,  B32B37/0084 ,  B32B37/02 ,  B32B37/04 ,  B32B38/04 ,  B32B38/10 ,  B32B2038/047 ,  B32B2307/202 ,  B32B2307/206 ,  B32B2311/00 ,  B32B2311/12 ,  B32B2457/00 ,  B32B2457/08 ,  H05K1/115 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/46 ,  H05K3/462 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/09918 ,  H05K2203/1536 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A manufacturing method of a circuit substrate includes the following steps. The peripheries of two metal layers are bonded to form a sealed area. Two insulating layers are formed on the two metal layers. Two including upper and bottom conductive layers are formed on the two insulating layers. Then, the two insulating layers and the two conductive layers are laminated so that the two metal layers bonded to each other are embedded between the two insulating layers. A part of the two insulating layers and a part of the two conductive layers are removed to form a plurality of blind holes exposing the two metal layers. A conductive material is formed in the blind holes and on the remained two conductive layers. The sealed area of the two metal layers is separated to form two separated circuit substrates.