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公开(公告)号：US07034514B2
公开(公告)日：2006-04-25
申请号：US10808532
申请日：2004-03-25
CPC分类号： G05F3/30
摘要： A semiconductor device is disclosed including a current generator circuit that generates a first current substantially proportional to an absolute temperature, the first current being determined by a size ratio of a MOS transistor, and by a resistor; and a starting-up circuit that causes the current generator circuit to generate the first current at a stable working point of the current generator circuit, wherein while the current generator circuit operates at the stable working point, a current that flows through the starting-up circuit is determined by a diffusion resistance and a MOS transistor. When the current generator circuit starts operating at a stable operating point, resistance of the diffusion resistor and a MOS transistor connected in series determines a current that flows through a starting-up circuit. According to the above arrangements, the power consumption of the circuit can be reduced by increasing the resistance of the diffused resistor.
摘要翻译： 公开了一种半导体器件，其包括电流发生器电路，其产生与绝对温度成正比的第一电流，第一电流由MOS晶体管的尺寸比和电阻器确定; 以及启动电路，其使得所述电流发生器电路在所述电流发生器电路的稳定工作点处产生所述第一电流，其中当所述电流发生器电路在所述稳定工作点处工作时，流过所述启动的电流 电路由扩散电阻和MOS晶体管决定。 当电流发生器电路在稳定工作点开始工作时，串联的扩散电阻器和MOS晶体管的电阻决定了流过启动电路的电流。 根据上述配置，可以通过增加扩散电阻器的电阻来降低电路的功耗。
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公开(公告)号：US20050088163A1
公开(公告)日：2005-04-28
申请号：US10808532
申请日：2004-03-25
CPC分类号： G05F3/30
摘要： A semiconductor device is disclosed including a current generator circuit that generates a first current substantially proportional to an absolute temperature, the first current being determined by a size ratio of a MOS transistor, and by a resistor; and a starting-up circuit that causes the current generator circuit to generate the first current at a stable working point of the current generator circuit, wherein while the current generator circuit operates at the stable working point, a current that flows through the starting-up circuit is determined by a diffusion resistance and a MOS transistor. When the current generator circuit starts operating at a stable operating point, resistance of the diffusion resistor and a MOS transistor connected in series determines a current that flows through a starting-up circuit. According to the above arrangements, the power consumption of the circuit can be reduced by increasing the resistance of the diffused resistor.
摘要翻译： 公开了一种半导体器件，其包括电流发生器电路，其产生与绝对温度成正比的第一电流，第一电流由MOS晶体管的尺寸比和电阻器确定; 以及启动电路，其使得所述电流发生器电路在所述电流发生器电路的稳定工作点处产生所述第一电流，其中当所述电流发生器电路在所述稳定工作点处工作时，流过所述启动的电流 电路由扩散电阻和MOS晶体管决定。 当电流发生器电路在稳定工作点开始工作时，串联的扩散电阻器和MOS晶体管的电阻决定了流过启动电路的电流。 根据上述配置，可以通过增加扩散电阻器的电阻来降低电路的功耗。
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公开(公告)号：US07586371B2
公开(公告)日：2009-09-08
申请号：US11589140
申请日：2006-10-30
申请人： Suguru Tachibana , Kenta Aruga , Tatsuo Kato
发明人： Suguru Tachibana , Kenta Aruga , Tatsuo Kato
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F3/347 , H03F3/45183 , H03F2200/453 , H03F2200/456 , H03F2203/45138 , H03F2203/45466
摘要： The present invention is contrived to adopt a differential pair type amplifier circuit comprising a differential pair constituted by a first transistor receiving an input of a first signal and by a second transistor receiving an input of a third signal generated by outputting a second signal of which the voltage level is a power supply voltage. Elements requiring a matching are two transistors constituting the differential pair for the amplifier circuit. Because of this, the elements requiring a matching can be placed close to each other regardless of a layout between the amplifier circuits.
摘要翻译： 本发明被设计为采用差分对型放大器电路，其包括由接收第一信号的输入的第一晶体管和由第二晶体管构成的差分对，所述第二晶体管接收通过输出第二信号而产生的第三信号的输入， 电压电平是电源电压。 需要匹配的元件是构成放大器电路的差分对的两个晶体管。 因此，不管放大器电路之间的布局如何，需要匹配的元件可以彼此靠近放置。
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公开(公告)号：US20070040600A1
公开(公告)日：2007-02-22
申请号：US11260176
申请日：2005-10-28
申请人： Suguru Tachibana , Kazuhiro Mitsuda , Tatsuo Kato
发明人： Suguru Tachibana , Kazuhiro Mitsuda , Tatsuo Kato
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A band gap circuit includes a voltage generating circuit, and a first and a second switched capacitor circuits (SCC). Operational amplifier in the first and the second SCC are connected though a coupling capacitor. Capacitance of the coupling capacitor is smaller than that of a feedback capacitor in the first SCC. A PTAT voltage is obtained by multiplying a thermal voltage by a coefficient determined based on capacitances of input capacitors and feedback capacitors in each of the first and the second SCC, and the coupling capacitor. The voltage generating circuit generates a forward bias voltage that has a negative temperature-dependency at a p-n junction. The PTAT voltage is added to the forward bias voltage to generate a reference voltage independent of temperature.
摘要翻译： 带隙电路包括电压产生电路和第一和第二开关电容器电路（SCC）。 第一和第二SCC中的运算放大器通过耦合电容器连接。 耦合电容的电容小于第一SCC中的反馈电容的电容。 通过将热电压乘以基于第一和第二SCC中的每一个中的输入电容器和反馈电容器的电容确定的系数和耦合电容器来获得PTAT电压。 电压产生电路产生在p-n结处具有负温度依赖性的正向偏置电压。 将PTAT电压加到正向偏置电压以产生独立于温度的参考电压。
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公开(公告)号：US07176740B2
公开(公告)日：2007-02-13
申请号：US10948524
申请日：2004-09-24
申请人： Suguru Tachibana , Tatsuo Kato
发明人： Suguru Tachibana , Tatsuo Kato
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K17/102 , H03K17/223
摘要： A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.
摘要翻译： 电平转换电路，在适当进行电平转换的同时，防止电源电压下降时的运转速度降低。 电平转换电路包括第一和第二PMOS晶体管。 第一NMOS晶体管连接到第一PMOS晶体管和第二PMOS晶体管。 第二NMOS晶体管连接到第二PMOS晶体管和第一PMOS晶体管。 连接到第一和第二NMOS晶体管的偏置电路产生提供给第一和第二NMOS晶体管并且大于第一电压的第一和第二NMOS晶体管的阈值电压的偏置电位。 偏置电路还根据具有第一电压的控制信号控制电流，该电流确定偏置电位并流向偏置电路。
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公开(公告)号：US20050237099A1
公开(公告)日：2005-10-27
申请号：US10948524
申请日：2004-09-24
申请人： Suguru Tachibana , Tatsuo Kato
发明人： Suguru Tachibana , Tatsuo Kato
CPC分类号： H03K3/356113 , H03K17/102 , H03K17/223
摘要： A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.
摘要翻译： 电平转换电路，在适当进行电平转换的同时，防止电源电压下降时的运转速度降低。 电平转换电路包括第一和第二PMOS晶体管。 第一NMOS晶体管连接到第一PMOS晶体管和第二PMOS晶体管。 第二NMOS晶体管连接到第二PMOS晶体管和第一PMOS晶体管。 连接到第一和第二NMOS晶体管的偏置电路产生提供给第一和第二NMOS晶体管并且大于第一电压的第一和第二NMOS晶体管的阈值电压的偏置电位。 偏置电路还根据具有第一电压的控制信号控制电流，该电流确定偏置电位并流向偏置电路。
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公开(公告)号：US20050052303A1
公开(公告)日：2005-03-10
申请号：US10774525
申请日：2004-02-10
申请人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
发明人： Suguru Tachibana , Tatsuo Kato , Hideo Nunokawa
摘要： An AD converter includes a sample-&-hold circuit which samples and holds an input analog potential in a first period, and generates a signal indicative of a magnitude relation between the held input analog potential and a reference potential in a second period, a plurality of amplifiers connected in series which amplify an output of the sample-&-hold circuit, and a control circuit which controls operating timing of the amplifiers so as to make at least one of the amplifiers start operating in a middle of the first period.
摘要翻译： AD转换器包括采样保持电路，其在第一周期中采样并保持输入模拟电位，并且产生指示在第二周期中保持的输入模拟电位与参考电位之间的大小关系的信号，多个 放大器连接的放大器，其放大采样保持电路的输出;以及控制电路，其控制放大器的工作时序，以使至少一个放大器在第一周期的中间开始工作。
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公开(公告)号：US20070252573A1
公开(公告)日：2007-11-01
申请号：US11589139
申请日：2006-10-30
申请人： Suguru Tachibana , Kenta Aruga , Tatsuo Kato
发明人： Suguru Tachibana , Kenta Aruga , Tatsuo Kato
IPC分类号： G05F3/16
CPC分类号： G05F3/30
摘要： A reference voltage generation circuit has transistors generating a PTAT current that increases in proportion to temperature, a transistor generating a CTAT current that decreases in proportion to temperature, a first variable resistor adjusting an output voltage, a transistor supplying the PTAT current to the first variable resistor via a first switch, a transistor supplying the CTAT current to the first variable resistor via a second switch, and a second variable resistor adjusting the CTAT current. The first switch is on in first and third operation modes and off in a second operation mode. The second switch is on in the first and second operation modes and off in the third operation mode. Switching the operation modes realizes independently outputting a PTAT voltage or a CTAT voltage. Independently adjusting the voltages makes it possible to correct output reference voltage of the reference voltage generation circuit accurately at low cost.
摘要翻译： 参考电压产生电路具有产生与温度成比例地增加的PTAT电流的晶体管，产生与温度成比例地降低的CTAT电流的晶体管，调节输出电压的第一可变电阻器，将PTAT电流提供给第一变量的晶体管 经由第一开关的电阻器，经由第二开关将CTAT电流提供给第一可变电阻器的晶体管，以及调节CTAT电流的第二可变电阻器。 在第一和第三操作模式下，第一开关处于开启状态，并在第二操作模式中关闭。 第二开关在第一和第二操作模式中接通，并且在第三操作模式中断开。 切换操作模式可实现独立输出PTAT电压或CTAT电压。 独立地调节电压可以以低成本准确地校正参考电压产生电路的输出参考电压。
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公开(公告)号：US07233273B2
公开(公告)日：2007-06-19
申请号：US11363968
申请日：2006-03-01
申请人： Suguru Tachibana , Kazuhiro Mitsuda , Tatsuo Kato
发明人： Suguru Tachibana , Kazuhiro Mitsuda , Tatsuo Kato
IPC分类号： H03M1/12
CPC分类号： H03M1/1023 , H03M1/0682 , H03M1/468 , H03M1/804
摘要： Included are a first unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the first analog signal, a second unit including a DAC which generates a comparison signal serving as an object of comparison with the first analog signal, taking in and retaining the second analog signal, a first switch connecting the first unit to an output side of the second unit, a comparator comparing a differential value between the first analog signal and the second analog signal with a differential value between the comparison signal of the first DAC and an output signal of the second DAC, and an electric potential control circuit controlling fluctuations in electric potentials of the first analog terminal and the second analog terminal.
摘要翻译： 包括第一单元，包括DAC，其产生用作与第一模拟信号进行比较的对象的比较信号，接收并保持第一模拟信号;第二单元，包括DAC，其产生用作对象的比较信号 与所述第一模拟信号进行比较，接收和保持所述第二模拟信号，将所述第一单元连接到所述第二单元的输出侧的第一开关，将所述第一模拟信号和所述第二模拟信号之间的差分值与 第一DAC的比较信号和第二DAC的输出信号之间的差分值以及控制第一模拟端子和第二模拟端子的电位波动的电位控制电路。
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公开(公告)号：US20070115041A1
公开(公告)日：2007-05-24
申请号：US11650485
申请日：2007-01-08
申请人： Suguru Tachibana , Tatsuo Kato
发明人： Suguru Tachibana , Tatsuo Kato
IPC分类号： H03L5/00
CPC分类号： H03K3/356113 , H03K17/102 , H03K17/223
摘要： A level conversion circuit that prevents the operation speed from decreasing when the power supply voltage decreases while appropriately performing level conversion. The level conversion circuit includes first and second PMOS transistors. A first NMOS transistor is connected to the first PMOS transistor and the second PMOS transistor. A second NMOS transistor is connected to the second PMOS transistor and the first PMOS transistor. A bias circuit, connected to the first and second NMOS transistors, generates a bias potential that is supplied to the first and second NMOS transistors and that is greater than the first voltage by a threshold voltage of the first and second NMOS transistors. The bias circuit further controls current, which determines the bias potential and flows to the bias circuit, in accordance with a control signal having the first voltage.
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