公开(公告)号：US5736435A

公开(公告)日：1998-04-07

申请号：US497317

申请日：1995-07-03

申请人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze ,  Sergio Ajuria

发明人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze ,  Sergio Ajuria

IPC分类号： H01L21/336 ,  H01L21/84 ,  H01L29/786 ,  H01L21/00 ,  H01L21/3205

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L29/78618 ,  H01L29/78648

摘要： A process for fabricating a MOSFET on an SOI substrate includes the formation of an active region (14) isolated by field isolation regions (16, 18) and by an insulating layer (12). A recess (26) is formed in the active region (14) using a masking layer (22) having an opening (24) therein. A gate dielectric layer (32) is formed in the recess (26) and a polycrystalline silicon layer (34) is deposited to overlie the masking layer (22), and to fill the recess (26). A planarization process is carried out to form a gate electrode (36) in the recess (26), and source and drain regions (40, 42) are formed in a self-aligned manner to the gate electrode (36). A channel region (44) resides intermediate to the source and drain regions (40, 42) and directly below the gate electrode (36).

摘要翻译： 在SOI衬底上制造MOSFET的工艺包括形成由场隔离区域（16,18）和绝缘层（12）隔离的有源区域（14）。 使用其中具有开口（24）的掩模层（22）在有源区域（14）中形成凹部（26）。 在凹部（26）中形成栅介电层（32），沉积多晶硅层（34）以覆盖掩模层（22）并填充凹部（26）。 进行平面化处理以在凹部（26）中形成栅电极（36），并且源极和漏极区域（40,42）以与栅电极（36）自对准的方式形成。 通道区域（44）位于源极和漏极区域（40,42）的中间，并且位于栅电极（36）的正下方。

公开(公告)号：US5459096A

公开(公告)日：1995-10-17

申请号：US270545

申请日：1994-07-05

申请人： Suresh Venkatesan ,  Stephen Poon

发明人： Suresh Venkatesan ,  Stephen Poon

IPC分类号： H01L21/3105 ,  H01L21/302

CPC分类号： H01L21/31053 ,  H01L21/31055 ,  Y10S148/005 ,  Y10S438/97

摘要： An improved planarization process includes the steps of forming recessed regions (38) and elevated regions (34) in a semiconductor substrate (30). The substrate is oxidized to form an oxide liner (39) overlying the recessed regions, and a fill material (40) is deposited to overlie the substrate (30) filling the recessed regions (38). An etching process is used to remove portions of the fill material (40) and to expose portions of a first planarization layer (44) overlying the elevated regions (34) of the substrate (30). The fill material is etched and a second planarization layer (46) is deposited to overlie dielectric portions (42), and portions (44) of first planarization layer (32) exposed by the etching process. A chemical-mechanical-polishing process is then carried out to form a planar surface (47), and remaining portions of the planarization layers and fill material are removed.

摘要翻译： 改进的平面化处理包括在半导体衬底（30）中形成凹陷区域（38）和升高区域（34）的步骤。 衬底被氧化以形成覆盖在凹陷区域上的氧化物衬垫（39），并且沉积填充材料（40）以覆盖填充凹陷区域（38）的衬底（30）。 蚀刻工艺用于去除填充材料（40）的部分并暴露覆盖衬底（30）的升高区域（34）的第一平坦化层（44）的部分。 蚀刻填充材料，并且沉积第二平坦化层（46）以覆盖介电部分（42）和通过蚀刻工艺暴露的第一平坦化层（32）的部分（44）。 然后进行化学机械抛光工艺以形成平坦表面（47），并且除去平坦化层和填充材料的剩余部分。

公开(公告)号：US5627097A

公开(公告)日：1997-05-06

申请号：US498709

申请日：1995-07-03

申请人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze

发明人： Suresh Venkatesan ,  Stephen Poon ,  Jeffrey Lutze

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/70

CPC分类号： H01L29/66575 ,  H01L21/823814

摘要： A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).

摘要翻译： 具有减小的寄生结电容的CMOS器件和用于制造器件的工艺。 该器件包括从形成在半导体衬底（12）中的掩埋层（16,18）垂直分离源区和漏区（52和53,54和55）的未掺杂外延层（20）的一部分（20'）。 未掺杂的外延层（20）通过提供本征硅区域来物理地分离来自源极和漏极区域的高掺杂剂浓度的区域，从而减小了源极和漏极区域的结电容。 另外，根据本发明制造的MOS晶体管具有从未掺杂的外延层（20）的上表面（22）延伸到位于半导体衬底（12）中的掩埋层（16,18）的完全自对准沟道区， 。

公开(公告)号：US09355910B2

公开(公告)日：2016-05-31

申请号：US13324740

申请日：2011-12-13

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/70 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/768 ,  H01L27/118

CPC分类号： H01L23/535 ,  H01L21/28518 ,  H01L21/76895 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/53238 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/0847 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

摘要翻译： 提供半导体器件用于实现至少一个逻辑元件。 该半导体器件包括具有第一晶体管的半导体衬底和形成在半导体衬底上的第二晶体管。 每个晶体管包括源极，漏极和栅极。 沟槽硅化物层将第一晶体管的源极或漏极之一电连接到第二晶体管的源极或漏极之一。

公开(公告)号：US20140042641A1

公开(公告)日：2014-02-13

申请号：US13568737

申请日：2012-08-07

申请人： Mahbub Rashed ,  Yuansheng Ma ,  Irene Lin ,  Jason Stephens ,  Yunfei Deng ,  Yuan Lei ,  Jongwook Kye ,  Rod Augur ,  Shibly Ahmed ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Yuansheng Ma ,  Irene Lin ,  Jason Stephens ,  Yunfei Deng ,  Yuan Lei ,  Jongwook Kye ,  Rod Augur ,  Shibly Ahmed ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L23/5386 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/5384 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

摘要： An approach for providing MOL constructs using diffusion contact structures is disclosed. Embodiments include: providing a first diffusion region in a substrate; providing, via a first lithography process, a first diffusion contact structure; providing, via a second lithography process, a second diffusion contact structure; and coupling the first diffusion contact structure to the first diffusion region and the second diffusion contact structure. Embodiments include: providing a second diffusion region in the substrate; providing a diffusion gap region between the first and second diffusion regions; providing the diffusion contact structure over the diffusion gap region; and coupling, via the diffusion contact structure, the first and second diffusion regions.

摘要翻译： 公开了一种使用扩散接触结构提供MOL构造的方法。 实施例包括：在衬底中提供第一扩散区域; 通过第一光刻工艺提供第一扩散接触结构; 经由第二光刻工艺提供第二扩散接触结构; 以及将所述第一扩散接触结构耦合到所述第一扩散区和所述第二扩散接触结构。 实施例包括：在衬底中提供第二扩散区域; 在所述第一和第二扩散区之间提供扩散间隙区域; 在扩散间隙区域上提供扩散接触结构; 以及经由扩散接触结构耦合第一和第二扩散区域。

公开(公告)号：US08621074B2

公开(公告)日：2013-12-31

申请号：US13458327

申请日：2012-04-27

申请人： Faiyaz Shikari ,  Madhav Matta ,  Suresh Venkatesan

发明人： Faiyaz Shikari ,  Madhav Matta ,  Suresh Venkatesan

IPC分类号： G06F15/173

CPC分类号： H04L43/08 ,  G06F9/546 ,  G06F2209/548 ,  H04L67/10 ,  H04L67/1002 ,  H04L67/1008

摘要： A management system for processing message-based communications comprising a plurality of servers configured to implement a plurality of sessions that process a plurality of messages, a plurality of message queues coupled to the servers and configured to exchange the messages with the servers, and a workload manager coupled to the servers and the message queues and configured to reallocate the sessions to the different servers and the corresponding message queues to achieve load balance between the servers and the message queues in a recurring manner during processing of the messages by the servers based on a depth of each of the message queues, a quantity of sessions for each of the servers, and a workload manager configuration.

摘要翻译： 一种用于处理基于消息的通信的管理系统，包括被配置为实现处理多个消息的多个会话的多个服务器，耦合到所述服务器并被配置为与所述服务器交换消息的多个消息队列，以及工作负载 管理器耦合到服务器和消息队列，并被配置为将会话重新分配到不同的服务器和相应的消息队列，以在服务器基于以下情况处理消息期间以重复的方式实现服务器和消息队列之间的负载平衡 每个消息队列的深度，每个服务器的会话数量以及工作负载管理器配置。

公开(公告)号：US08618607B1

公开(公告)日：2013-12-31

申请号：US13539830

申请日：2012-07-02

申请人： Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  David Doman ,  Marc Tarabbia ,  Irene Lin ,  Jeff Kim ,  Chinh Nguyen ,  Steve Soss ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/02

CPC分类号： H01L27/0207 ,  H01L27/11807

摘要： One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

摘要翻译： 本文公开的一个说明性器件包括限定在半导体衬底中的连续有源区，形成在连续有源区中和上方的第一和第二晶体管，第一和第二晶体管中的每一个包括形成在连续有源区中的多个掺杂区， 导电隔离电极位于第一和第二晶体管之间的连续有源区上方，导电隔离电极与导电隔离电极导电耦合。

公开(公告)号：US08598633B2

公开(公告)日：2013-12-03

申请号：US13351101

申请日：2012-01-16

申请人： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Marc Tarabbia ,  James B. Gullette ,  Mahbub Rashed ,  David S. Doman ,  Irene Y. Lin ,  Ingolf Lorenz ,  Larry Ho ,  Chinh Nguyen ,  Jeff Kim ,  Jongwook Kye ,  Yuansheng Ma ,  Yunfei Deng ,  Rod Augur ,  Seung-Hyun Rhee ,  Jason E. Stephens ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L23/52

CPC分类号： H01L23/5286 ,  H01L21/76895 ,  H01L21/823475 ,  H01L27/088 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

摘要翻译： 半导体器件包括具有扩散区域的半导体衬底。 晶体管形成在扩散区内。 电力轨设置在扩散区域的外侧。 接触层设置在基板上方和电源轨下方。 通孔设置在接触层和电源轨之间以将接触层电连接到电源轨。 接触层包括设置在扩散区域外部的第一长度和从第一长度延伸到扩散区域并电连接到晶体管的第二长度。

公开(公告)号：US20190326219A1

公开(公告)日：2019-10-24

申请号：US16502521

申请日：2019-07-03

申请人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub Rashed ,  Irene Y. Lin ,  Steven Soss ,  Jeff Kim ,  Chinh Nguyen ,  Marc Tarabbia ,  Scott Johnson ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L23/535 ,  H01L29/08 ,  H01L27/092 ,  H01L23/532 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/285 ,  H01L27/02 ,  H01L21/768

摘要： A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.

公开(公告)号：US20140183638A1

公开(公告)日：2014-07-03

申请号：US13729843

申请日：2012-12-28

申请人： Mahbub RASHED ,  Srikanth Samavedam ,  David Doman ,  Navneet Jain ,  Subramani Kengeri ,  Suresh Venkatesan

发明人： Mahbub RASHED ,  Srikanth Samavedam ,  David Doman ,  Navneet Jain ,  Subramani Kengeri ,  Suresh Venkatesan

IPC分类号： H01L21/84 ,  H01L27/12

CPC分类号： H01L21/845 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211

摘要： Methodology enabling selectively connecting fin structures using a segmented trench salicide layer, and the resulting device are disclosed. Embodiments include: providing on a substrate at least one gate structure; providing first and second fin structures in a vertical direction intersecting with the at least one gate structure; and providing a first segment of a salicide layer, the first segment being formed along a horizontal direction and being connected with the second fin structure and separated from the first fin structure.

摘要翻译： 公开了使用分段沟槽自对准硅层选择性地连接翅片结构的方法，以及所得到的装置。 实施例包括：在衬底上提供至少一个栅极结构; 在与所述至少一个栅极结构相交的垂直方向上提供第一和第二鳍结构; 以及提供自对准层的第一段，所述第一段沿着水平方向形成并且与所述第二鳍结构连接并与所述第一鳍结构分离。