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    Underlayer composition and method of manufacturing a semiconductor device
    1.
    发明授权
    Underlayer composition and method of manufacturing a semiconductor device 有权

    公开(公告)号：US12099301B2

    公开(公告)日：2024-09-24

    申请号：US17231402

    申请日：2021-04-15

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    发明人： Chien-Chih Chen

    IPC分类号： G03F7/11 ,  G03F7/004 ,  G03F7/20 ,  H01L21/027

    CPC分类号： G03F7/11 ,  G03F7/0045 ,  H01L21/0274 ,  G03F7/0042 ,  G03F7/2004

    摘要： A method of manufacturing a semiconductor device includes forming a photoresist underlayer over a semiconductor substrate. The photoresist underlayer includes a polymer, including a main polymer chain having pendant target groups, and pendant organic groups or photoacid generator groups. The main polymer chain is a polystyrene, a polyhydroxystyrene, a polyacrylate, a polymethylacrylate, a polymethylmethacrylate, a polyacrylic acid, a polyvinyl ester, a polymaleic ester, a poly(methacrylonitrile), or a poly(methacrylamide). Pendant target groups are selected from the group consisting of a substituted or unsubstituted: C2-C30 diol group, C1-C30 aldehyde group, and C3-C30 ketone group. Pendant organic groups are C3-C30 aliphatic or aromatic groups having at least one photosensitive functional group, and pendant photoacid generator groups are C3-C50 substituted aliphatic or aromatic groups. A photoresist layer is formed over the photoresist underlayer. The photoresist layer is selectively exposed to actinic radiation. The selectively exposed photoresist layer is developed to form a photoresist pattern.

    Dummy insertion for improving throughput of electron beam lithography
    2.
    发明授权
    Dummy insertion for improving throughput of electron beam lithography 有权

    公开(公告)号：US11526081B2

    公开(公告)日：2022-12-13

    申请号：US17366319

    申请日：2021-07-02

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

    IPC分类号： G03F7/20 ,  G03F1/36 ,  G03F1/78

    摘要： An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

    Dummy Insertion for Improving Throughput of Electron Beam Lithography
    3.
    发明申请
    Dummy Insertion for Improving Throughput of Electron Beam Lithography 有权

    公开(公告)号：US20210405534A1

    公开(公告)日：2021-12-30

    申请号：US17366319

    申请日：2021-07-02

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Shih-Ming Chang ,  Wen Lo ,  Chun-Hung Liu ,  Chia-Hua Chang ,  Hsin-Wei Wu ,  Ta-Wei Ou ,  Chien-Chih Chen ,  Chien-Cheng Chen

    IPC分类号： G03F7/20 ,  G03F1/36

    摘要： An electron beam lithography system and an electron beam lithography process are disclosed herein for improving throughput. An exemplary method for increasing throughput achieved by an electron beam lithography system includes receiving an integrated circuit (IC) design layout that includes a target pattern, wherein the electron beam lithography system implements a first exposure dose to form the target pattern on a workpiece based on the IC design layout. The method further includes inserting a dummy pattern into the IC design layout to increase a pattern density of the IC design layout to greater than or equal to a threshold pattern density, thereby generating a modified IC design layout. The electron beam lithography system implements a second exposure dose that is less than the first exposure dose to form the target pattern on the workpiece based on the modified IC design layout.

    Mask Blank for Scattering Effect Reduction
    6.
    发明申请
    Mask Blank for Scattering Effect Reduction 有权
    掩模空白用于散射效应减少

    公开(公告)号：US20140255825A1

    公开(公告)日：2014-09-11

    申请号：US13788105

    申请日：2013-03-07

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO. LTD.

    发明人： Chih-Chiang Tu ,  Chun-Lang Chen ,  Jong-Yuh Chang ,  Chien-Chih Chen ,  Chen-Shao Hsu

    IPC分类号： G03F1/20

    CPC分类号： G03F1/20

    摘要： Some embodiments relate a method of forming a photomask for a deep ultraviolet photolithography process (e.g., having an exposing radiation with a wavelength of 193 nm). The method provides a mask blank for a deep ultraviolet photolithography process. The mask blank has a transparent substrate, an amorphous isolation layer located over the transparent substrate, and a photoresist layer located over the amorphous isolation layer. The photoresist layer is patterned by selectively removing portions of the photoresist layer using a beam of electrons. The amorphous isolation layer is subsequently etched according to the patterned photoresist layer to form one or more mask openings. The amorphous isolation layer isolates electrons backscattered from the beam of electrons from the photoresist layer during patterning, thereby mitigating CD and overlay errors caused by backscattered electrons.

    摘要翻译： 一些实施例涉及形成用于深紫外光刻工艺（例如，具有193nm的波长的曝光辐射）的光掩模的方法。 该方法提供用于深紫外光刻工艺的掩模坯料。 掩模坯料具有透明基板，位于透明基板上方的非晶隔离层以及位于非晶隔离层之上的光致抗蚀剂层。 通过使用电子束选择性去除光致抗蚀剂层的部分来对光致抗蚀剂层进行构图。 随后根据图案化的光致抗蚀剂层蚀刻非晶隔离层以形成一个或多个掩模开口。 非晶隔离层在图案化期间将电子反向散射的电子与光致抗蚀剂层隔离，从而减轻CD和由背散射电子引起的重叠误差。

    Mask overlay control
    9.
    发明授权
    Mask overlay control 有权
    面膜叠加控制

    公开(公告)号：US09377701B2

    公开(公告)日：2016-06-28

    申请号：US14696596

    申请日：2015-04-27

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Chih-Chiang Tu ,  Chun-Lang Chen ,  Jong-Yuh Chang ,  Chien-Chih Chen ,  Chen-Shao Hsu

    IPC分类号： G03F1/22 ,  G03F1/70 ,  G03F7/20 ,  G03F9/00

    CPC分类号： G03F7/70783 ,  G03F1/22 ,  G03F1/70 ,  G03F9/7069

    摘要： In some embodiments, a mask patterning system includes an electronic memory configured to store an integrated circuit mask layout. A computation tool determines a number of radiation shots to be used to write the integrated circuit mask layout to a physical mask. The computation tool also determines a scaling factor which accounts for expected thermal expansion of the physical mask due to the number of radiation shots used in writing the integrated circuit mask layout to the physical mask. An ebeam or laser writing tool writes the integrated circuit mask layout to the physical mask based on the scaling factor and by using the number of radiation shots.

    摘要翻译： 在一些实施例中，掩模图案形成系统包括被配置为存储集成电路掩模布局的电子存储器。 计算工具确定用于将集成电路掩模布局写入物理掩模的多个辐射照射。 计算工具还确定了由于在将集成电路掩模布局写入物理掩模中使用的辐射照射的数量而导致物理掩模的预期热膨胀的缩放因子。 ebeam或激光写入工具根据缩放因子和使用辐射数量将集成电路掩模布局写入物理掩模。