公开(公告)号：US12080604B2

公开(公告)日：2024-09-03

申请号：US18362163

申请日：2023-07-31

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien-Jung Hung

IPC分类号： H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/78696

摘要： A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US12046276B2

公开(公告)日：2024-07-23

申请号：US18306757

申请日：2023-04-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chuan Yang ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Ping-Wei Wang

IPC分类号： G11C11/412 ,  H10B10/00

CPC分类号： G11C11/412 ,  H10B10/12

摘要： One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.

公开(公告)号：US20240153949A1

公开(公告)日：2024-05-09

申请号：US18404234

申请日：2024-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang ,  Wen-Chun Keng ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC分类号： H01L27/0921 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/4238

摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.

公开(公告)号：US11908910B2

公开(公告)日：2024-02-20

申请号：US16949363

申请日：2020-10-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chuan Yang ,  Jing-Yi Lin ,  Hsin-Wen Su ,  Shih-Hao Lin

IPC分类号： H01L29/417 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H10B10/00 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/41791 ,  H01L21/823431 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78696 ,  H10B10/125

摘要： Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure.

公开(公告)号：US20230371225A1

公开(公告)日：2023-11-16

申请号：US18358562

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Ping-Wei Wang ,  Lien-Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan LIN ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC分类号： H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H04N21/426

CPC分类号： H10B10/12 ,  H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H10B10/00 ,  H01L22/12 ,  H10B41/35 ,  H04N21/42692 ,  H01L2924/1437 ,  G11C2213/79 ,  G11C2213/74

摘要： A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

公开(公告)号：US11605638B2

公开(公告)日：2023-03-14

申请号：US17342154

申请日：2021-06-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Hao Lin ,  Kian-Long Lim ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chia-Wei Chen ,  Chien-Chih Lin

IPC分类号： H01L27/11 ,  H01L29/40 ,  H01L29/423

摘要： Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

公开(公告)号：US20230067988A1

公开(公告)日：2023-03-02

申请号：US17460620

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Jing-Yi Lin ,  Shang-Rong Li ,  Chong-De Lien

IPC分类号： H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762

摘要： A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.

公开(公告)号：US12087633B2

公开(公告)日：2024-09-10

申请号：US17464398

申请日：2021-09-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Chuan Yang ,  Chia-Hao Pao ,  Kuo-Hsiu Hsu ,  Shih-Hao Lin ,  Shang-Rong Li ,  Ping-Wei Wang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823418 ,  H01L21/823412

摘要： A method of forming a semiconductor structure includes forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, forming cladding layers along sidewalls of the fin structure, forming a dummy gate stack over the cladding layers, and forming source/drain (S/D) features in the fin structure and adjacent to the dummy gate stack. The method further includes removing the dummy gate stack to form a gate trench adjacent to the S/D features, removing the cladding layers to form first openings along the sidewalls of the fin structure, where the first openings extend to below the stack, removing the first semiconductor layers to form second openings between the second semiconductor layers and adjacent to the first openings, and subsequently forming a metal gate stack in the gate trench, the first openings, and the second openings.

公开(公告)号：US12016169B2

公开(公告)日：2024-06-18

申请号：US17842208

申请日：2022-06-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ping-Wei Wang ,  Lien Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan Lin ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC分类号： H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H04N21/426 ,  H10B10/00 ,  H10B41/35

CPC分类号： H10B10/12 ,  G11C11/412 ,  G11C11/419 ,  H01L22/12 ,  H01L23/528 ,  H04N21/42692 ,  H10B10/00 ,  H10B41/35 ,  G11C2213/74 ,  G11C2213/79 ,  H01L2924/1437

摘要： A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells includes a substrate having a front side and a back side with a transistor of the memory cell being formed on the front side and the back side being opposite of the front side, a first interconnect layer on the front side to provide a bit line of the memory cell, a second interconnect layer on the front side to provide a word line of the memory cell, a third interconnect layer on the back side to provide a supply voltage to the memory cell and a fourth interconnect layer on the back side to provide a ground voltage to the memory cell, widths of the bit line and the word line being chosen to reduce current-resistance drop.

公开(公告)号：US11996484B2

公开(公告)日：2024-05-28

申请号：US17319695

申请日：2021-05-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Hao Lin ,  Chih-Hsuan Chen ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chih-Yu Hsu ,  Hsin-Wen Su ,  Chia-Wei Chen

IPC分类号： H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66

CPC分类号： H01L29/78621 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/167 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78696 ,  H01L29/0665 ,  H01L29/456

摘要： A semiconductor device includes a substrate, two source/drain features over the substrate, channel layers connecting the two source/drain features, and a gate structure wrapping around each of the channel layers. Each of the two source/drain features include a first epitaxial layer, a second epitaxial layer over the first epitaxial layer, and a third epitaxial layer on inner surfaces of the second epitaxial layer. The channel layers directly interface with the second epitaxial layers and are separated from the third epitaxial layers by the second epitaxial layers. The first epitaxial layers include a first semiconductor material with a first dopant. The second epitaxial layers include the first semiconductor material with a second dopant. The second dopant has a higher mobility than the first dopant.