公开(公告)号：US20240397694A1

公开(公告)日：2024-11-28

申请号：US18788409

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chih-Hsiang Huang ,  Shang-Rong Li ,  Chih-Chuan Yang ,  Jui-Lin Chen ,  Ming-Shuan Li

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor structure includes a substrate, first channel layers vertically stacked over the substrate in a first region, and second channel layers vertically stacked over the substrate in a second region. The first and second regions have opposite conductivity types. The semiconductor structure also includes a threshold voltage (Vt) modulation layer wrapping around each of the second channel layers in the second region. The first region is free of the Vt modulation layer. The semiconductor structure also includes a gate dielectric layer wrapping around each of the first channel layers and the second channel layers over the Vt modulation layer, and a work function metal layer disposed on the gate dielectric layer and wrapping around each of the first channel layers and the second channel layers.

公开(公告)号：US12080604B2

公开(公告)日：2024-09-03

申请号：US18362163

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Wei Lee ,  Chien-Yuan Chen ,  Jo-Chun Hung ,  Yung-Hsiang Chan ,  Yu-Kuan Lin ,  Lien-Jung Hung

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/823431 ,  H01L21/823412 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/7851 ,  H01L29/78696

Abstract: A method includes providing a substrate, a dummy fin, and a stack of semiconductor channel layers; forming an interfacial layer wrapping around each of the semiconductor channel layers; depositing a high-k dielectric layer, wherein a first portion of the high-k dielectric layer over the interfacial layer is spaced away from a second portion of the high-k dielectric layer on sidewalls of the dummy fin by a first distance; depositing a first dielectric layer over the dummy fin and over the semiconductor channel layers, wherein a merge-critical-dimension of the first dielectric layer is greater than the first distance thereby causing the first dielectric layer to be deposited in a space between the dummy fin and a topmost layer of the stack of semiconductor channel layers, thereby providing air gaps between adjacent layers of the stack of semiconductor channel layers and between the dummy fin and the stack of semiconductor channel layers.

公开(公告)号：US12046276B2

公开(公告)日：2024-07-23

申请号：US18306757

申请日：2023-04-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chuan Yang ,  Feng-Ming Chang ,  Kuo-Hsiu Hsu ,  Ping-Wei Wang

IPC: G11C11/412 ,  H10B10/00

CPC classification number: G11C11/412 ,  H10B10/12

Abstract: One aspect of this description relates to a memory cell. In some embodiments, the memory cell includes a first gate structure, a second gate structure, a third gate structure, a fourth gate structure, and a fifth gate structure that each extend along a first lateral direction, a first active structure extending along a second lateral direction and overlaid by respective first portions of the first to fourth gate structures, a second active structure extending along the second lateral direction and overlaid by respective second portions of the first to fourth gate structures, and a third active structure extending along the second lateral direction and overlaid by respective third portions of the third and fifth gate structures. In some embodiments, the first and second gate structures are aligned with each other, with the fourth and fifth gate structures aligned with a first segment and a second segment of the third gate structure, respectively. In some embodiments, the second lateral direction perpendicular to the first lateral direction.

公开(公告)号：US20240153949A1

公开(公告)日：2024-05-09

申请号：US18404234

申请日：2024-01-04

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Wen Su ,  Lien Jung Hung ,  Ping-Wei Wang ,  Wen-Chun Keng ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L27/0921 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/4238

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip (IC). The method includes forming a first fin of semiconductor material and a second fin of semiconductor material within a semiconductor substrate. A gate structure is formed over the first fin and source/drain regions are formed on or within the first fin. The source/drain regions are formed on opposite sides of the gate structure. One or more pick-up regions are formed on or within the second fin. The source/drain regions respectively have a first width measured along a first direction parallel to a long axis of the first fin and the one or more pick-up regions respectively have a second width measured along the first direction. The second width is larger than the first width.

公开(公告)号：US11908910B2

公开(公告)日：2024-02-20

申请号：US16949363

申请日：2020-10-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Chuan Yang ,  Jing-Yi Lin ,  Hsin-Wen Su ,  Shih-Hao Lin

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L29/423 ,  H10B10/00 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/41791 ,  H01L21/823431 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/78696 ,  H10B10/125

Abstract: Methods and devices that provide a first fin structure, a second fin structure, and a third fin structure disposed over a substrate. A dielectric fin is formed between the first fin structure and the second fin structure, and a conductive line is formed between the second fin structure and the third fin structure.

公开(公告)号：US20230371225A1

公开(公告)日：2023-11-16

申请号：US18358562

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Ping-Wei Wang ,  Lien-Jung Hung ,  Kuo-Hsiu Hsu ,  Kian-Long Lim ,  Yu-Kuan LIN ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Choh Fei Yeap

IPC: H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H01L21/66 ,  H04N21/426

CPC classification number: H10B10/12 ,  H01L23/528 ,  G11C11/412 ,  G11C11/419 ,  H10B10/00 ,  H01L22/12 ,  H10B41/35 ,  H04N21/42692 ,  H01L2924/1437 ,  G11C2213/79 ,  G11C2213/74

Abstract: A memory device includes a memory array having a plurality of memory cells. Each memory cell of the plurality of memory cells is connected to a word line to apply a first signal to select the memory cell to read data from or write the data to the memory cell and a bit line to read the data from the memory cell or provide the data to write to the memory cell upon selecting the memory cell by the word line. A first bit line portion of the bit line connected to a first memory cell of the plurality of memory cells abuts a second bit line portion of the bit line connected to a second memory cell of the plurality of memory cells. The first memory cell is adjacent to the second memory cell.

公开(公告)号：US11605638B2

公开(公告)日：2023-03-14

申请号：US17342154

申请日：2021-06-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Kian-Long Lim ,  Chia-Hao Pao ,  Chih-Chuan Yang ,  Chia-Wei Chen ,  Chien-Chih Lin

IPC: H01L27/11 ,  H01L29/40 ,  H01L29/423

Abstract: Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.

公开(公告)号：US20230067988A1

公开(公告)日：2023-03-02

申请号：US17460620

申请日：2021-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Hao Lin ,  Chih-Chuan Yang ,  Hsin-Wen Su ,  Jing-Yi Lin ,  Shang-Rong Li ,  Chong-De Lien

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a protruding portion of a substrate, isolation features disposed over the substrate, wherein a top surface of the protruding portion of the substrate is separated from a bottom surface of the isolation features by a first distance, a metal gate stack interleaved with the stack of semiconductor layers, where a bottom portion of the metal gate stack is disposed on sidewalls of the protruding portion of the substrate and where thickness of the bottom portion of the metal gate stack is defined by a second distance that is less than the first distance, and epitaxial source/drain features disposed adjacent to the metal gate stack.

公开(公告)号：US12191306B2

公开(公告)日：2025-01-07

申请号：US17840913

申请日：2022-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jing-Yi Lin ,  Chih-Chuan Yang ,  Shih-Hao Lin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/02

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming an epitaxial structure having a first doping type over a first portion of a semiconductor substrate. A second portion of the semiconductor substrate is formed over the epitaxial structure and the first portion of the semiconductor substrate. A first doped region having the first doping type is formed in the second portion of the semiconductor substrate and directly over the epitaxial structure. A second doped region having a second doping type opposite the first doping type is formed in the second portion of the semiconductor substrate, where the second doped region is formed on a side of the epitaxial structure. A plurality of fins of the semiconductor substrate are formed by selectively removing portions of the second portion of the semiconductor substrate.

公开(公告)号：US20240379801A1

公开(公告)日：2024-11-14

申请号：US18782515

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Hao Pao ,  Chih-Chuan Yang ,  Shih-Hao Lin ,  Kian-Long Lim ,  Chih-Hsuan Chen ,  Ping-Wei Wang

IPC: H01L29/423 ,  H01L21/265 ,  H01L21/308 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.