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公开(公告)号：US12096621B2
公开(公告)日：2024-09-17
申请号：US17680208
申请日：2022-02-24
发明人： Wei Cheng Wu , Li-Feng Teng
CPC分类号： H10B41/00 , G11C16/0408 , H01L29/66825 , H01L29/788 , H10B12/09 , H10B12/50 , H10B99/00
摘要： Various embodiments of the present application are directed to an IC device and associated forming methods. In some embodiments, a memory region and a logic region are integrated in a substrate. A memory cell structure is disposed on the memory region. A plurality of logic devices disposed on a plurality of logic sub-regions of the logic region. A first logic device is disposed on a first upper surface of a first logic sub-region. A second logic device is disposed on a second upper surface of a second logic sub-region. A third logic device is disposed on a third upper surface of a third logic sub-region. Heights of the first, second, and third upper surfaces of the logic sub-regions monotonically decrease. By arranging logic devices on multiple recessed positions of the substrate, design flexibility is improved and devices with multiple operation voltages are better suited.
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公开(公告)号：US12058856B2
公开(公告)日：2024-08-06
申请号：US18231427
申请日：2023-08-08
发明人： Wei Cheng Wu , Li-Feng Teng
IPC分类号： H10B41/42 , H01L21/28 , H01L29/423 , H01L29/66 , H10B41/30 , H10B41/35 , H10B41/44 , H10B41/47 , H10B41/48 , H10B43/30
CPC分类号： H10B41/42 , H01L29/40114 , H01L29/42328 , H01L29/42344 , H01L29/66545 , H10B41/30 , H10B41/35 , H10B41/44 , H10B41/47 , H10B41/48 , H10B43/30
摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
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公开(公告)号：US12015029B2
公开(公告)日：2024-06-18
申请号：US18365424
申请日：2023-08-04
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Li-Feng Teng , Li-Jung Liu
IPC分类号： H01L27/088 , H01L29/06 , H01L29/417
CPC分类号： H01L27/0886 , H01L29/0649 , H01L29/41791
摘要： Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
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公开(公告)号：US20220285344A1
公开(公告)日：2022-09-08
申请号：US17751958
申请日：2022-05-24
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Li-Feng Teng , Li-Jung Liu
IPC分类号： H01L27/088 , H01L29/417 , H01L29/06
摘要： Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
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公开(公告)号：US20240071911A1
公开(公告)日：2024-02-29
申请号：US18162071
申请日：2023-01-31
发明人： Harry-Haklay Chuang , Wen-Tuo Huang , Li-Feng Teng , Wei-Cheng Wu , Yu-Jen Wang
IPC分类号： H01L23/522 , H01L23/00 , H01L23/64 , H01L25/065
CPC分类号： H01L23/5227 , H01L23/645 , H01L24/32 , H01L25/0657 , H01L2224/32145 , H01L2225/06524 , H01L2225/06527
摘要： A semiconductor device includes a first die having a first bonding layer; a second die having a second bonding layer disposed over and bonded to the first bonding layer; a plurality of bonding members, wherein each of the plurality of bonding members extends within the first bonding layer and the second bonding layer, wherein the plurality of bonding members includes a connecting member electrically connected to a first conductive pattern in the first die and a second conductive pattern in the second die, and a dummy member electrically isolated from the first conductive pattern and the second conductive pattern; and an inductor disposed within the first bonding layer and the second bonding layer. A method of manufacturing a semiconductor device includes bonding a first inductive coil of a first die to a second inductive coil of a second die to form an inductor.
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公开(公告)号：US20240021614A1
公开(公告)日：2024-01-18
申请号：US18365424
申请日：2023-08-04
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Li-Feng Teng , Li-Jung Liu
IPC分类号： H01L27/088 , H01L29/06 , H01L29/417
CPC分类号： H01L27/0886 , H01L29/0649 , H01L29/41791
摘要： Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
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公开(公告)号：US11830875B2
公开(公告)日：2023-11-28
申请号：US17751958
申请日：2022-05-24
发明人： Harry-Hak-Lay Chuang , Wei Cheng Wu , Li-Feng Teng , Li-Jung Liu
IPC分类号： H01L27/088 , H01L29/06 , H01L29/417
CPC分类号： H01L27/0886 , H01L29/0649 , H01L29/41791
摘要： Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.
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公开(公告)号：US11742348B2
公开(公告)日：2023-08-29
申请号：US17183564
申请日：2021-02-24
发明人： Li-Feng Teng , Wei-Cheng Wu , Harry-Hak-Lay Chuang , Li-Jung Liu
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/66
CPC分类号： H01L27/0886 , H01L21/823431 , H01L21/823456 , H01L21/823468 , H01L29/6656
摘要： A semiconductor device includes a substrate, a first gate structure and a second gate structure, a first gate spacer and a second gate spacer. The first gate spacer includes a first layer, a second layer over the first layer, a third layer over the second layer, a fourth layer over the third layer, and a fifth layer of the fourth layer, in which the first layer, the third layer, and the fifth layer of the first gate spacer are made of a same material. The second gate spacer includes a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer and the third layer of the second gate spacer are made of a same material, and in which a lateral width of the first gate spacer is greater than a lateral width of the second gate spacer.
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公开(公告)号：US11600618B2
公开(公告)日：2023-03-07
申请号：US17206076
申请日：2021-03-18
发明人： Harry-Hak-Lay Chuang , Li-Feng Teng , Wei-Cheng Wu , Fang-Lan Chu , Ya-Chen Kao
IPC分类号： H01L27/092 , H01L29/08 , H01L29/423 , H01L29/417 , H01L29/49 , H01L29/78 , H01L21/28 , H01L21/8238 , H01L29/66 , H01L27/11
摘要： A includes depositing a gate electrode layer over a semiconductor substrate; patterning the gate electrode layer into a first gate electrode and a gate electrode extending portion; forming a first gate spacer alongside the first gate electrode; patterning the gate electrode extending portion into a second gate electrode after forming the first gate spacer; and forming a second gate spacer alongside the second gate electrode and a third gate spacer around the first spacer.
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公开(公告)号：US12127399B2
公开(公告)日：2024-10-22
申请号：US18323458
申请日：2023-05-25
发明人： Meng-Han Lin , Te-Hsin Chiu , Wei-Cheng Wu , Li-Feng Teng , Chien-Hung Chang
IPC分类号： H01L29/06 , H01L21/28 , H01L21/762 , H01L21/765 , H01L23/00 , H01L29/40 , H01L29/66 , H10B20/00 , H10B41/35 , H10B41/43 , H10B41/49
CPC分类号： H10B20/60 , H01L21/76229 , H01L21/765 , H01L23/562 , H01L29/0649 , H01L29/40114 , H01L29/404 , H01L29/66825 , H10B41/35 , H10B41/43 , H10B41/49
摘要： A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.
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