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公开(公告)号：US11901387B2
公开(公告)日：2024-02-13
申请号：US17369567
申请日：2021-07-07
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Wen-Chang Kuo , Sheng-Chau Chen , Feng-Chi Hung , Sheng-Chan Li
IPC分类号： H01L27/146 , H01L21/762
CPC分类号： H01L27/1463 , H01L21/76224 , H01L27/14621 , H01L27/14627 , H01L27/14683
摘要： A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.
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公开(公告)号：US20230373018A1
公开(公告)日：2023-11-23
申请号：US17750951
申请日：2022-05-23
发明人： Ming-Che Lee , Kuo-Ming Wu , Sheng-Chau Chen , Ping-Tzu Chen
IPC分类号： B23C3/12 , H01L23/00 , H01L21/304 , B23C3/34
CPC分类号： B23C3/12 , H01L24/83 , H01L21/3043 , B23C3/34 , H01L2224/83947 , H01L2924/35121 , H01L24/32 , H01L2224/32145
摘要： In some embodiments, the present disclosure relates to a method that includes bonding a first wafer to a second wafer to form a wafer stack and removing a top portion of the second wafer. A first trim blade having a first blade width is aligned over the second wafer. The first trim blade is used to form a trench that separates a central portion of the second wafer from a peripheral portion of the second wafer. The trench is arranged at a first distance from an outer perimeter of the second wafer, and extends from a top surface of the second wafer to a trench depth beneath the top surface of the first wafer. A second trim blade having a second blade width is aligned over the peripheral portion, the second blade width being greater than the first blade width. The peripheral portion is removed using the second trim blade.
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公开(公告)号：US20230352438A1
公开(公告)日：2023-11-02
申请号：US17888569
申请日：2022-08-16
发明人： Kuo-Ming Wu , Hau-Yi Hsiao , Ping-Tzu Chen , Chung-Jen Huang , Sheng-Chau Chen
IPC分类号： H01L23/00
CPC分类号： H01L24/80 , H01L23/562 , H01L24/08 , H01L2224/08145 , H01L2224/80007 , H01L2224/80895 , H01L2224/80896 , H01L2924/3512 , H01L2924/35121
摘要： Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.
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公开(公告)号：US11682652B2
公开(公告)日：2023-06-20
申请号：US17197254
申请日：2021-03-10
IPC分类号： H01L23/00 , H01L23/544 , H01L25/065 , H01L21/02 , H01L21/67
CPC分类号： H01L24/94 , H01L21/02164 , H01L21/67121 , H01L23/544 , H01L24/80 , H01L25/0657 , H01L2224/80007 , H01L2224/80132 , H01L2224/80895 , H01L2224/80896
摘要： Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method comprises forming a plurality of semiconductor devices over a central region of a semiconductor wafer. The semiconductor wafer comprises a peripheral region laterally surrounding the central region and a circumferential edge disposed within the peripheral region. The semiconductor wafer comprises a notch disposed along the circumferential edge. Forming a stack of inter-level dielectric (ILD) layers over the semiconductor devices and laterally within the central region. Forming a bonding support structure over the peripheral region such that the bonding support structure comprises a bonding structure notch disposed along a circumferential edge of the bonding support structure. Forming the bonding support structure includes disposing the semiconductor wafer over a lower plasma exclusion zone (PEZ) ring that comprises a PEZ ring notch disposed along a circumferential edge of the lower PEZ ring.
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公开(公告)号：US11605534B2
公开(公告)日：2023-03-14
申请号：US17371577
申请日：2021-07-09
发明人： Tung-He Chou , Sheng-Chau Chen , Ming-Tung Wu , Hsun-Chung Kuang
IPC分类号： H01L21/02 , B08B5/02 , H01L21/687 , H01L21/67 , B08B3/10
摘要： In some embodiments, the present disclosure relates to method for trimming and cleaning an edge of a wafer. The method includes trimming an outer edge portion of the wafer with a blade along a continuously connected trim path to define a new sidewall of the wafer. The trimming produces contaminant particles on the wafer. Further, the method includes applying deionized water to the new sidewall of the wafer with water nozzles to remove the contaminant particles. The method also includes applying pressurized gas to the wafer at a first top surface area of the wafer with an air jet nozzle. The pressurized gas is directed outward from a center of the wafer to remove remaining contaminant particles. The applying of deionized water and the applying of pressurized gas are performed in a same chamber as the trimming.
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公开(公告)号：US11594679B2
公开(公告)日：2023-02-28
申请号：US17406214
申请日：2021-08-19
IPC分类号： H01L45/00
摘要： The problem of forming top electrode vias that provide consistent results in devices that include resistance switching RAM cells of varying heights is solved using a dielectric composite that fills areas between resistance switching RAM cells and varies in height to align with the tops of both the taller and the shorter resistance switching RAM cells. An etch stop layer may be formed over the dielectric composite providing an equal thickness of etch-resistant dielectric over both taller and shorter resistance switching RAM cells. The dielectric composite causes the etch stop layer to extend laterally away from the resistance switching RAM cells to maintain separation between the via openings and the resistance switching RAM cell sides even when the openings are misaligned.
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公开(公告)号：US20220278144A1
公开(公告)日：2022-09-01
申请号：US17369567
申请日：2021-07-07
发明人： Min-Feng Kao , Dun-Nian Yaung , Jen-Cheng Liu , Wen-Chang Kuo , Sheng-Chau Chen , Feng-Chi Hung , Sheng-Chan Li
IPC分类号： H01L27/146 , H01L21/762
摘要： A semiconductor device according to the present disclosure includes a semiconductor layer, a plurality of metal isolation features disposed in the semiconductor layer, a metal grid disposed directly over the plurality of metal isolation features, and a plurality of microlens features disposed over the metal grid.
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公开(公告)号：US10522514B2
公开(公告)日：2019-12-31
申请号：US16102501
申请日：2018-08-13
发明人： Kuo-Ming Wu , Yung-Lung Lin , Zhi-Yang Wang , Sheng-Chau Chen , Cheng-Hsien Chou
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00
摘要： A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.
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公开(公告)号：US20190013295A1
公开(公告)日：2019-01-10
申请号：US16102501
申请日：2018-08-13
发明人： Kuo-Ming Wu , Yung-Lung Lin , Zhi-Yang Wang , Sheng-Chau Chen , Cheng-Hsien Chou
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
摘要： A structure and a method of forming are provided. The structure includes a first dielectric layer overlying a first substrate. A first connection pad is disposed in a top surface of the first dielectric layer and contacts a first redistribution line. A first dummy pad is disposed in the top surface of the first dielectric layer, the first dummy pad contacting the first redistribution line. A second dielectric layer overlies a second substrate. A second connection pad and a second dummy pad are disposed in the top surface of the second dielectric layer, the second connection pad bonded to the first connection pad, and the first dummy pad positioned in a manner that is offset from the second dummy pad so that the first dummy pad and the second dummy pad do not contact each other.
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公开(公告)号：US20180068965A1
公开(公告)日：2018-03-08
申请号：US15800491
申请日：2017-11-01
发明人： Sheng-Chau Chen , Shih Pei Chou , Yen-Chang Chu , Cheng-Hsien Chou , Chih-Hui Huang , Yeur-Luen Tu
IPC分类号： H01L23/00 , H01L21/321 , H01L21/324 , H01L21/311 , H01L25/065 , H01L27/146
CPC分类号： H01L24/08 , H01L21/31144 , H01L21/3212 , H01L21/324 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/80 , H01L25/0657 , H01L27/14634 , H01L27/1464 , H01L27/1469 , H01L2224/02321 , H01L2224/0235 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/03614 , H01L2224/03845 , H01L2224/039 , H01L2224/05553 , H01L2224/05554 , H01L2224/05555 , H01L2224/05556 , H01L2224/05557 , H01L2224/05559 , H01L2224/05569 , H01L2224/05576 , H01L2224/05647 , H01L2224/05687 , H01L2224/08057 , H01L2224/08145 , H01L2224/08147 , H01L2224/80011 , H01L2224/80013 , H01L2224/80121 , H01L2224/80895 , H01L2224/80896 , H01L2224/80906 , H01L2224/80948 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/05042 , H01L2924/05442 , H01L2924/059 , H01L2924/00014 , H01L2924/00012 , H01L2924/04642
摘要： A representative device includes a patterned opening through a layer at a surface of a device die. A liner is disposed on sidewalls of the opening and the device die is patterned to extend the opening further into the device die. After patterning, the liner is removed. A conductive pad is formed in the device die by filling the opening with a conductive material.
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