公开(公告)号：US11932534B2

公开(公告)日：2024-03-19

申请号：US17696299

申请日：2022-03-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Hua Lin ,  Chang-Ming Wu ,  Chung-Yi Yu ,  Ping-Yin Liu ,  Jung-Huei Peng

IPC: B81C1/00 ,  B81B7/00 ,  H01L23/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81C1/00333 ,  H01L24/09 ,  H01L24/89 ,  B81B2207/07 ,  B81C2201/0132 ,  B81C2203/0109 ,  B81C2203/0785 ,  B81C2203/0792 ,  H01L2224/091 ,  H01L2224/80013 ,  H01L2224/80895

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

公开(公告)号：US20220204340A1

公开(公告)日：2022-06-30

申请号：US17696299

申请日：2022-03-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Hua Lin ,  Chang-Ming Wu ,  Chung-Yi Yu ,  Ping-Yin Liu ,  Jung-Huei Peng

IPC: B81C1/00 ,  B81B7/00 ,  H01L23/00

Abstract: A microelectromechanical system (MEMS) structure and method of forming the MEMS device, including forming a first metallization structure over a complementary metal-oxide-semiconductor (CMOS) wafer, where the first metallization structure includes a first sacrificial oxide layer and a first metal contact pad. A second metallization structure is formed over a MEMS wafer, where the second metallization structure includes a second sacrificial oxide layer and a second metal contact pad. The first metallization structure and second metallization structure are then bonded together. After the first metallization structure and second metallization structure are bonded together, patterning and etching the MEMS wafer to form a MEMS element over the second sacrificial oxide layer. After the MEMS element is formed, removing the first sacrificial oxide layer and second sacrificial oxide layer to allow the MEMS element to move freely about an axis.

公开(公告)号：US20200052082A1

公开(公告)日：2020-02-13

申请号：US16657293

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming Chyi Liu ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Wei Cheng Wu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai ,  Ru-Liang Lee

IPC: H01L29/423 ,  H01L27/11521 ,  H01L29/66 ,  H01L21/28

Abstract: An exemplary method includes forming a common source region in a substrate, and forming an isolation feature over the common source region. The common source region is disposed between the substrate and the isolation feature. The common source region and the isolation feature span a plurality of active regions of the substrate. A gate, such as an erase gate, may be formed after forming the common source region. In some implementations, the common source region is formed by etching the substrate to form a saw-tooth shaped recess region (or a U-shaped recess region) and performing an ion implantation process to form a doped region in a portion of the saw-tooth shaped recess region (or the U-shaped recess region), such that the common source region has a sawtooth profile (or a U-shaped profile).

公开(公告)号：US20190241425A1

公开(公告)日：2019-08-08

申请号：US16390709

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Lee-Chuan Tseng ,  Chang-Ming Wu ,  Shih-Chang Liu ,  Yuan-Chih Hsieh

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/001 ,  B81C1/0092 ,  B81C1/00936 ,  B81C1/00944 ,  B81C1/00952 ,  B81C1/0096 ,  B81C1/00984 ,  B81C1/00992 ,  B81C2201/0132 ,  B81C2201/056

Abstract: The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.

公开(公告)号：US10048220B2

公开(公告)日：2018-08-14

申请号：US14878999

申请日：2015-10-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shih-Wei Lin ,  Chang-Ming Wu ,  Lee-Chuan Tseng ,  Shih-Chang Liu

IPC: G01N27/414

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a gate structure over a first surface of the substrate, and a source region and a drain region in the substrate adjacent to the gate structure. The semiconductor structure further comprises a channel region interposing the source and drain regions and underlying the gate structure. The semiconductor structure further comprises a first layer over a second surface of the substrate opposite to the first surface, and a second layer over the first layer. The semiconductor structure further comprises a sensing film over the channel region and at least a portion of the first and second layers, and a well over the sensing film and cutting off the first layer and the second layer.

公开(公告)号：US09978759B2

公开(公告)日：2018-05-22

申请号：US15355624

申请日：2016-11-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Harry-Hak-Lay Chuang

IPC: H01L21/336 ,  H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/11517 ,  H01L27/11568 ,  H01L29/792 ,  H01L27/11519 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L21/823456 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A method comprises forming a memory gate structure adjacent to a control gate structure over a substrate, wherein a charge storage layer is between the memory gate structure and the control gate structure and a top surface of the memory gate structure is covered by a gate mask layer, forming a first spacer along sidewalls of the memory gate structure and the gate mask layer, wherein a sidewall of the memory gate structure is fully covered by the first spacer, applying an etching process to the charge storage layer to form an L-shaped charge storage layer and forming a first drain/source region adjacent to the memory gate structure and a second drain/source region adjacent to the control gate structure.

公开(公告)号：US20150311296A1

公开(公告)日：2015-10-29

申请号：US14794682

申请日：2015-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Harry-Hak-Lay Chuang

IPC: H01L29/423 ,  H01L29/792 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28282 ,  H01L21/823456 ,  H01L27/11517 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/792

Abstract: A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer over a top surface of the memory gate structure, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.

公开(公告)号：US20240057346A1

公开(公告)日：2024-02-15

申请号：US18150863

申请日：2023-01-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fu-Ting Sung ,  Tsung-Hsueh Yang ,  Chang-Ming Wu ,  Chang-Chih Huang ,  Yu-Wen Wang ,  Kuo-Chyuan Tzeng

IPC: H10B63/10 ,  H10N70/00

CPC classification number: H10B63/10 ,  H10N70/841 ,  H10N70/8828 ,  H10N70/063 ,  H10N70/021

Abstract: Device structures and methods for forming the same are provided. A device structure according to the present disclosure includes a first electrode and a second electrode disposed over an etch stop layer (ESL), a first dielectric layer disposed between the first electrode and the second electrode, a phase-change material layer disposed over the first electrode, the first dielectric layer and the second electrode, an insulator layer disposed over the phase-change material layer, a metal feature disposed over the insulator layer, and a second dielectric layer disposed over the insulator layer, the first electrode, the second electrode, and the metal feature.

公开(公告)号：US20230363285A1

公开(公告)日：2023-11-09

申请号：US18353254

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Min-Yung Ko ,  Chern-Yow Hsu ,  Chang-Ming Wu ,  Shih-Chang Liu

IPC: H10N50/01 ,  H10B61/00 ,  H10B63/00 ,  H10N50/10 ,  H10N50/80 ,  H10N70/00

CPC classification number: H10N50/01 ,  H10B61/22 ,  H10B63/30 ,  H10N50/10 ,  H10N50/80 ,  H10N70/021 ,  H10N70/063 ,  H10N70/068 ,  H10N70/841

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a memory cell. In some embodiments, a memory film is deposited over a substrate and comprises a bottom electrode layer, a top electrode layer, and a data storage film between the top and bottom electrode layers. A hard mask film is deposited over the memory film and comprises a conductive hard mask layer. The top electrode layer and the hard mask film are patterned to respectively form a top electrode and a hard mask over the top electrode. A trimming process is performed to decrease a sidewall angle between a sidewall of the hard mask and a bottom surface of the hard mask. An etch is performed into the data storage film with the hard mask in place after the trimming process to form a data storage structure underlying the top electrode.

公开(公告)号：US10665600B2

公开(公告)日：2020-05-26

申请号：US15413256

申请日：2017-01-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chang-Ming Wu ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Harry-Hak-Lay Chuang ,  Chia-Shiung Tsai

IPC: H01L27/11568 ,  H01L29/792 ,  H01L29/423 ,  H01L21/311 ,  H01L29/66

Abstract: A device comprises a control gate structure and a memory gate structure over a substrate, a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure.