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公开(公告)号：US11282697B2
公开(公告)日：2022-03-22
申请号：US16569019
申请日：2019-09-12
发明人： Xin-Hua Huang , Ping-Yin Liu , Hung-Hua Lin , Hsun-Chung Kuang , Yuan-Chih Hsieh , Lan-Lin Chao , Chia-Shiung Tsai , Xiaomeng Chen
IPC分类号： B23K1/00 , H01L21/02 , B23K1/20 , B23K20/02 , B23K20/233 , B23K20/24 , H01L23/00 , B23K101/40 , B23K101/42
摘要： A method includes performing a plasma activation on a surface of a first package component, removing oxide regions from surfaces of metal pads of the first package component, and performing a pre-bonding to bond the first package component to a second package component.
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公开(公告)号：US10384933B2
公开(公告)日：2019-08-20
申请号：US15643536
申请日：2017-07-07
发明人： Chun-wen Cheng , Hung-Chia Tsai , Lan-Lin Chao , Yuan-Chih Hsieh , Ping-Yin Liu
IPC分类号： B81C1/00
摘要： A method of making a micro electromechanical system (MEMS) package includes patterning a substrate to form a MEMS section. The method further includes bonding a carrier to a surface of the substrate. The carrier is free of active devices. The carrier includes a carrier bond pad on a surface of the carrier opposite the MEMS section. The carrier bond pad is electrically connected to the MEMS section. The method further includes bonding a wafer bond pad of an active circuit wafer to the carrier bond pad. The bonding of the wafer bond pad to the carrier bond pad includes re-graining the wafer bond pad to form at least one grain boundary extending from the wafer bond pad to the carrier bond pad.
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公开(公告)号：US20190100431A1
公开(公告)日：2019-04-04
申请号：US16046651
申请日：2018-07-26
发明人： Chih-Ming Chen , Yuan-Chih Hsieh , Chung-Yi Yu
IPC分类号： B81C1/00 , H01L25/00 , B81B7/00 , H01L23/488
摘要： The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
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公开(公告)号：US09337168B2
公开(公告)日：2016-05-10
申请号：US14174214
申请日：2014-02-06
发明人： Richard Chu , Martin Liu , Chia-Hua Chu , Yuan-Chih Hsieh , Chung-Hsien Lin , Lan-Lin Chao , Chun-Wen Cheng , Mingo Liu
CPC分类号： H01L24/94 , B81B2207/015 , B81C1/00269 , B81C2203/0109 , B81C2203/0771 , H01L23/481 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/1306 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.
摘要翻译： 提供晶圆级封装。 该封装包括具有晶体管器件的第一半导体晶片和包括第一材料的第一结合层。 所述封装包括具有第二接合层的第二半导体晶片，所述第二接合层包括不同于所述第一材料的第二材料，所述第一和第二材料中的一个为铝基，另一个为钛基。 其中第二晶片的一部分通过第一和第二接合层扩散地结合到第一晶片。
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公开(公告)号：US20150332968A1
公开(公告)日：2015-11-19
申请号：US14809664
申请日：2015-07-27
发明人： Yuan-Chih Hsieh , Li-Cheng Chu , Ming-Tung Wu , Ping-Yin Liu , Lan-Lin Chao , Chia-Shiung Tsai
IPC分类号： H01L21/768 , H01L25/065 , H01L25/00
CPC分类号： H01L23/5384 , H01L21/76802 , H01L21/76831 , H01L21/7684 , H01L21/7685 , H01L21/76877 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2225/06548 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides various embodiments of a via structure and method of manufacturing same. In an example, a via structure includes a via having via sidewall surfaces defined by a semiconductor substrate. The via sidewall surfaces have a first portion and a second portion. A conductive layer is disposed in the via on the first portion of the via sidewall surfaces, and a dielectric layer is disposed on the second portion of the via sidewall surfaces. The dielectric layer is disposed between the second portion of the via sidewall surfaces and the conductive layer. In an example, the dielectric layer is an oxide layer.
摘要翻译： 本公开提供了通孔结构及其制造方法的各种实施例。 在一个示例中，通孔结构包括具有由半导体衬底限定的通孔侧壁表面的通孔。 通孔侧壁表面具有第一部分和第二部分。 在通路侧壁表面的第一部分上的通路中设置导电层，并且介电层设置在通孔侧壁表面的第二部分上。 电介质层设置在通孔侧壁表面的第二部分和导电层之间。 在一个实例中，电介质层是氧化物层。
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公开(公告)号：US11814283B2
公开(公告)日：2023-11-14
申请号：US17349156
申请日：2021-06-16
发明人： Kuei-Sung Chang , Chun-Wen Cheng , Fei-Lung Lai , Shing-Chyang Pan , Yuan-Chih Hsieh , Yi-Ren Wang
CPC分类号： B81B3/0013 , B81C1/00984 , B81B2203/04 , B81B2207/07
摘要： Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.
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公开(公告)号：US20230357002A1
公开(公告)日：2023-11-09
申请号：US18357019
申请日：2023-07-21
发明人： Chih-Ming Chen , Yuan-Chih Hsieh , Chung-Yi Yu
IPC分类号： B81C1/00 , H01L23/488 , H01L25/00 , B81B7/00
CPC分类号： B81C1/00269 , H01L23/488 , H01L25/50 , B81C1/00238 , B81C1/00 , B81B7/0041 , B81B2201/0242 , B81B2207/012 , B81B2201/0264 , B81C2203/035 , B81C2203/0118 , B81B2201/0235 , H01L24/81
摘要： The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.
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8.发明授权公开(公告)号：US11697588B2
公开(公告)日：2023-07-11
申请号：US17542679
申请日：2021-12-06
发明人： Yi-Ren Wang , Shing-Chyang Pan , Yuan-Chih Hsieh
CPC分类号： B81B7/02 , B81C1/00047 , B81C1/00095 , B81C1/00277 , B81B2201/0235 , B81B2201/0242
摘要： Various embodiments of the present disclosure are directed towards a method for manufacturing an integrated chip, the method comprises forming an interconnect structure over a semiconductor substrate. An upper dielectric layer is formed over the interconnect structure. An outgas layer is formed within the upper dielectric layer. The outgas layer comprises a first material that is amorphous. A microelectromechanical systems (MEMS) substrate is formed over the interconnect structure. The MEMS substrate comprises a moveable structure directly over the outgas layer.
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公开(公告)号：US20190241425A1
公开(公告)日：2019-08-08
申请号：US16390709
申请日：2019-04-22
CPC分类号： B81B3/001 , B81C1/0092 , B81C1/00936 , B81C1/00944 , B81C1/00952 , B81C1/0096 , B81C1/00984 , B81C1/00992 , B81C2201/0132 , B81C2201/056
摘要： The present disclosure involves forming a method of fabricating a Micro-Electro-Mechanical System (MEMS) device. A plurality of openings is formed in a first side of a first substrate. A dielectric layer is formed over the first side of the substrate. A plurality of segments of the dielectric layer fills the openings. The first side of the first substrate is bonded to a second substrate that contains a cavity. The bonding is performed such that the segments of the dielectric layer are disposed over the cavity. A portion of the first substrate disposed over the cavity is transformed into a plurality of movable components of a MEMS device. The movable components are in physical contact with the dielectric the layer. Thereafter, a portion of the dielectric layer is removed without using liquid chemicals.
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公开(公告)号：US09873610B2
公开(公告)日：2018-01-23
申请号：US13929623
申请日：2013-06-27
发明人： Chung-Hsien Lin , Chia-Hua Chu , Li-Cheng Chu , Yuan-Chih Hsieh , Chun-Wen Cheng
CPC分类号： B81B7/0032 , B81B2207/092 , B81C1/00269 , B81C1/00357 , B81C2203/0109 , B81C2203/0792 , H01L2924/0002 , H01L2924/00
摘要： A MEMS device is described. The device includes a micro-electro-mechanical systems (MEMS) substrate including a first bonding layer, a semiconductor substrate including a second bonding layer, and a cap including a third bonding layer, the cap coupled to the semiconductor substrate by bonding the second bonding layer to the third bonding layer. The first bonding layer includes silicon, the semiconductor substrate is electrically coupled to the MEMS substrate by bonding the first bonding layer to the second bonding layer, and the MEMS substrate is hermetically sealed between the cap and the semiconductor substrate.
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