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公开(公告)号：US20190051628A1
公开(公告)日：2019-02-14
申请号：US16160572
申请日：2018-10-15
Inventor： Ping-Yin Liu , Shih-Wei Lin , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/74 , H01L24/94 , H01L2224/02215 , H01L2224/0361 , H01L2224/03616 , H01L2224/0381 , H01L2224/05647 , H01L2224/05687 , H01L2224/08145 , H01L2224/74 , H01L2224/7501 , H01L2224/75101 , H01L2224/7565 , H01L2224/75753 , H01L2224/75824 , H01L2224/80 , H01L2224/80004 , H01L2224/80007 , H01L2224/8001 , H01L2224/80011 , H01L2224/80013 , H01L2224/80014 , H01L2224/80065 , H01L2224/80075 , H01L2224/80097 , H01L2224/80121 , H01L2224/80136 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/83889 , H01L2224/94 , H01L2924/00014 , H01L2924/1461 , H01L2924/351 , Y10T156/15 , Y10T156/1744 , H01L2924/00012 , H01L2924/05442 , H01L2924/00
Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
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公开(公告)号：US20170358551A1
公开(公告)日：2017-12-14
申请号：US15689982
申请日：2017-08-29
Inventor： Ping-Yin Liu , Shih-Wei Lin , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
IPC: H01L23/00
CPC classification number: H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/74 , H01L24/94 , H01L2224/02215 , H01L2224/0361 , H01L2224/03616 , H01L2224/0381 , H01L2224/05647 , H01L2224/05687 , H01L2224/08145 , H01L2224/74 , H01L2224/7501 , H01L2224/75101 , H01L2224/7565 , H01L2224/75753 , H01L2224/75824 , H01L2224/80004 , H01L2224/80007 , H01L2224/8001 , H01L2224/80011 , H01L2224/80013 , H01L2224/80014 , H01L2224/80065 , H01L2224/80075 , H01L2224/80097 , H01L2224/80121 , H01L2224/80136 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/83889 , H01L2224/94 , H01L2924/00014 , H01L2924/1461 , H01L2924/351 , Y10T156/15 , Y10T156/1744 , H01L2924/00012 , H01L2224/80 , H01L2924/05442 , H01L2924/00
Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
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公开(公告)号：US09748198B2
公开(公告)日：2017-08-29
申请号：US14725266
申请日：2015-05-29
Inventor： Ping-Yin Liu , Shih-Wei Lin , Xin-Hua Huang , Lan-Lin Chao , Chia-Shiung Tsai
CPC classification number: H01L24/80 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/27 , H01L24/74 , H01L24/94 , H01L2224/02215 , H01L2224/0361 , H01L2224/03616 , H01L2224/0381 , H01L2224/05647 , H01L2224/05687 , H01L2224/08145 , H01L2224/74 , H01L2224/7501 , H01L2224/75101 , H01L2224/7565 , H01L2224/75753 , H01L2224/75824 , H01L2224/80004 , H01L2224/80007 , H01L2224/8001 , H01L2224/80011 , H01L2224/80013 , H01L2224/80014 , H01L2224/80065 , H01L2224/80075 , H01L2224/80097 , H01L2224/80121 , H01L2224/80136 , H01L2224/80203 , H01L2224/80895 , H01L2224/80896 , H01L2224/83889 , H01L2224/94 , H01L2924/00014 , H01L2924/1461 , H01L2924/351 , Y10T156/15 , Y10T156/1744 , H01L2924/00012 , H01L2224/80 , H01L2924/05442 , H01L2924/00
Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
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公开(公告)号：US09567208B1
公开(公告)日：2017-02-14
申请号：US14935318
申请日：2015-11-06
Inventor： Chun-Wen Cheng , Yi-Chuan Teng , Cheng-Yu Hsieh , Lee-Chuan Tseng , Shih-Wei Lin
CPC classification number: B81B7/008 , B81B3/0005 , B81B7/0041 , B81B2201/02 , B81B2207/012 , B81C1/00277 , B81C1/00293 , B81C2203/0145 , B81C2203/0172 , B81C2203/019 , B81C2203/0792 , H01L2224/11
Abstract: A semiconductor structure includes a first device, a second device, a first hole, a second hole, and a sealing object. The second device is contacted to the first device, wherein a chamber is formed between the first device and the second device. The first hole is disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference. The second hole is disposed in the second device and aligned to the first hole. The sealing object seals the second hole. The first end links with the chamber, and the first circumference is different from the second circumference.
Abstract translation: 半导体结构包括第一器件，第二器件，第一孔，第二孔和密封件。 第二装置与第一装置接触，其中在第一装置和第二装置之间形成一个室。 第一孔设置在第二装置中并限定在具有第一圆周的第一端和具有第二圆周的第二端之间。 第二孔设置在第二装置中并与第一孔对准。 密封件密封第二个孔。 第一端与腔室连接，第一圆周与第二圆周不同。
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公开(公告)号：US20150330942A1
公开(公告)日：2015-11-19
申请号：US14810255
申请日：2015-07-27
Inventor： Yi-Hsien Chang , Chun-Ren Cheng , Shih-Wei Lin , Yi-Shao Liu
IPC: G01N27/414 , H01L21/3213 , H01L21/768 , H01L21/285 , H01L21/8234 , H01L21/311
CPC classification number: G01N27/4145 , H01L21/28525 , H01L21/31111 , H01L21/32135 , H01L21/7684 , H01L21/76877 , H01L21/823437 , H01L21/823475 , H01L27/283
Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device includes a plurality of micro wells having a sensing gate bottom and a number of stacked well portions. A bottom surface area of a well portion is different from a top surface area of a well portion directly below. The micro wells are formed by multiple etching operations through different materials, including a sacrificial plug, to expose the sensing gate without plasma induced damage.
Abstract translation: 本公开提供了生物场效应晶体管（BioFET）和制造BioFET器件的方法。 该方法包括使用与互补金属氧化物半导体（CMOS）工艺兼容或典型的一个或多个工艺步骤形成BioFET。 BioFET器件包括具有感测栅极底部和多个堆叠阱部分的多个微孔。 井部的底面积与直接在下方的井口部的顶面积不同。 微孔通过不同材料的多次蚀刻操作形成，包括牺牲塞，以暴露感测门而不产生等离子体的损伤。
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Patent Agency Ranking
公开(公告)号：US20250048753A1
公开(公告)日：2025-02-06
申请号：US18924056
申请日：2024-10-23
Inventor： Yung-Chang Chang , Shih-Wei Lin , Te-Hsien Hsieh , Jung-I Lin
IPC: H01L27/146
Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material. A second semiconductor material is disposed on the substrate. A doped region is between the substrate and a part of the second semiconductor material. The second semiconductor material includes a projection extending outward from a surface of the second semiconductor material and towards the photodiode region. The projection extends through the doped region.
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公开(公告)号：US20240372018A1
公开(公告)日：2024-11-07
申请号：US18775697
申请日：2024-07-17
Inventor： Chen-Hao Chiang , Shih-Wei Lin , Eugene I-Chun Chen , Yi-Chen Chen
IPC: H01L31/0232 , G02B6/12 , G02B6/124 , G02B6/13 , G02B6/136 , H01L31/028 , H01L31/18
Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a first doped region disposed in a semiconductor substrate and a second doped region disposed in the semiconductor substrate. A photodetector is disposed between the first doped region and the second doped region. The photodetector has a lower surface that arcs between opposing sidewalls of the photodetector in a cross-sectional view. The first doped region and the second doped region contact the lower surface of the photodetector.
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公开(公告)号：US20150084099A1
公开(公告)日：2015-03-26
申请号：US14033089
申请日：2013-09-20
Inventor： Wei-Cheng Shen , Yi-Hsien Chang , Shih-Wei Lin , Chun-Ren Cheng
IPC: G01N27/414
CPC classification number: G01N27/4145 , G01N27/4148
Abstract: The present disclosure provides a biological field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET includes a microwells having a sensing layer, a top metal stack under the sensing layer, and a multi-layer interconnect (MLI) under the top metal stack. The top metal stack includes a top metal and a protective layer over and peripherally surrounding the top metal.
Abstract translation: 本公开提供了生物场效应晶体管（BioFET）和制造BioFET器件的方法。 该方法包括使用与互补金属氧化物半导体（CMOS）工艺兼容或典型的一个或多个工艺步骤形成BioFET。 BioFET包括具有感测层的微孔，感测层下的顶部金属堆叠，以及在顶部金属堆叠下的多层互连（MLI）。 顶部金属堆叠包括顶部金属和保护层，并且围绕顶部金属周围。
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公开(公告)号：US20240379400A1
公开(公告)日：2024-11-14
申请号：US18782200
申请日：2024-07-24
Inventor： Ting-Jung Chen , Shih-Wei Lin , Lee-Chuan Tseng
IPC: H01L21/683 , C23C14/50 , C23C14/54 , C23C14/58 , C23C16/458 , C23C16/46 , H01J37/32 , H01L21/67 , H01L21/768
Abstract: In some embodiments, the present disclosure relates to a process tool that includes a chamber housing defined by a processing chamber, and a wafer chuck structure arranged within the processing chamber. The wafer chuck structure is configured to hold a wafer during a fabrication process. The wafer chuck includes a lower portion and an upper portion arranged over the lower portion. The lower portion includes trenches extending from a topmost surface towards a bottommost surface of the lower portion. The upper portion includes openings that are holes, extend completely through the upper portion, and directly overlie the trenches of the lower portion. Multiple of the openings directly overlie each trench. Further, cooling gas piping is coupled to the trenches of the lower portion of the wafer chuck structure, and a cooling gas source is coupled to the cooling gas piping.
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公开(公告)号：US11434129B2
公开(公告)日：2022-09-06
申请号：US15407676
申请日：2017-01-17
Inventor： Chun-Wen Cheng , Yi-Chuan Teng , Cheng-Yu Hsieh , Lee-Chuan Tseng , Shih-Chang Liu , Shih-Wei Lin
Abstract: A semiconductor structure includes: a first device; a second device contacted with the first device, wherein a chamber is formed between the first device and the second device; a first hole disposed in the second device and defined between a first end with a first circumference and a second end with a second circumference; a second hole disposed in the second device and aligned to the first hole; and a sealing object for sealing the second hole. The first end links with the chamber, and the first circumference is different from the second circumference, the second hole is defined between the second end and a third end with a third circumference, and the second circumference and the third circumference are smaller than the first circumference.
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