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公开(公告)号：US10002829B2
公开(公告)日：2018-06-19
申请号：US14954207
申请日：2015-11-30
发明人： Hao Chen , Chen-Hsiang Hsu , Hung-Chih Lin , Ching-Nen Peng , Mill-Jer Wang
IPC分类号： H01L23/528 , G01R19/00 , G01R31/28 , H01L23/31 , H01L23/00 , H01L25/065 , H01L23/498
CPC分类号： H01L23/528 , G01R19/0092 , G01R31/2831 , G01R31/2884 , G01R31/2896 , H01L22/32 , H01L23/3107 , H01L23/49816 , H01L23/49827 , H01L24/06 , H01L24/09 , H01L24/14 , H01L24/17 , H01L25/0655 , H01L2224/02371 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/13024 , H01L2224/24137 , H01L2924/18162 , H01L2924/2064
摘要： A semiconductor device is provided which comprises a semiconductive substrate and an interconnect on the substrate. The interconnect comprises a dielectric in an upper most level of the interconnect and a plurality of conductive pads where each of the plurality of conductive pads is at least partially exposed from the dielectric. The interconnect further includes a current sensor electrically coupled with at least one of the plurality of conductive pads.
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公开(公告)号：US20140176165A1
公开(公告)日：2014-06-26
申请号：US13724004
申请日：2012-12-21
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Chung-Han Huang , Chung-Sheng Yuan , Ching-Fang Chen , Wen-Wen Hsieh , Meng-Lin Chung
IPC分类号： G01R31/26
CPC分类号： G01R31/2889 , G01R1/07378
摘要： A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit.
摘要翻译： 三维集成电路测试装置包括：探针卡，被配置为将三维集成电路的测试装置与具有多个测试模块的自动测试设备板耦合，其中所述探针卡包括多个已知的 三维集成电路的良好裸片，三维集成电路的多个互连和多个探针触点，其中探针触点被配置为将探针卡与被测器件的测试触点耦合 三维集成电路。
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公开(公告)号：US09915699B2
公开(公告)日：2018-03-13
申请号：US14488852
申请日：2014-09-17
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Mincent Lee , Chen-Hung Tien , Chang Chia How
CPC分类号： G01R31/2893 , G01R3/00 , G01R31/2891 , G01R31/2894
摘要： A method of probe testing dies, the method includes loading a wafer having a first die and a second die into a prober and bringing probes of the prober into contact with first contact pads of the first die according to first probe parameters. A first probe contact test of first values of the contact between the probes and the first contact pads is performed, and a die test of the first die is performed after performing the probe contact test. Results of the die test and results of the probe contact test are saved and second probe parameters are automatically generated based on at least the results of the first probe contact test.
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公开(公告)号：US09859176B1
公开(公告)日：2018-01-02
申请号：US15339309
申请日：2016-10-31
发明人： Tang-Jung Chiu , Mill-Jer Wang , Hung-Chih Lin , Hao Chen
CPC分类号： H01L22/22 , G01R1/06772 , G01R31/2822 , G01R31/2886 , H01L22/34 , H01L23/5256 , H01L23/66 , H01L2223/6672
摘要： A semiconductor device is disclosed. The semiconductor device includes: a System on Chip (SoC) die; an integrated passive device (IPD); and a first switch, coupled between the SoC die and the IPD; wherein the IPD and the SoC die are disposed in different wafers and bonded together, and the first switch is controlled to disconnect the IPD from the SoC die when the IPD is under a test; and the first switch is controlled to connect the IPD with the SoC die when the IPD is not under the test. A test system for testing an IPD of a semiconductor device and an associated method are also disclosed.
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公开(公告)号：US20150380328A1
公开(公告)日：2015-12-31
申请号：US14845786
申请日：2015-09-04
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
CPC分类号： H01L22/32 , H01L22/14 , H01L22/30 , H01L22/34 , H01L23/544 , H01L24/11 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2223/54406 , H01L2223/5442 , H01L2223/54426 , H01L2223/54433 , H01L2223/54473 , H01L2224/16148 , H01L2224/16225 , H01L2224/16238 , H01L2224/17051 , H01L2224/1712 , H01L2224/81193 , H01L2225/06596
摘要： A package component includes a stack-probe unit, which includes a first-type connector, and a second-type connector connected to the first-type connector. The first-type connector and the second-type connector are exposed through a surface of the package component.
摘要翻译： 包装组件包括堆叠探针单元，其包括第一类型连接器和连接到第一类型连接器的第二类型连接器。 第一型连接器和第二型连接器通过封装部件的表面露出。
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公开(公告)号：US11387683B2
公开(公告)日：2022-07-12
申请号：US17015602
申请日：2020-09-09
发明人： Min-Jer Wang , Ching-Nen Peng , Chewn-Pu Jou , Feng Wei Kuo , Hao Chen , Hung-Chih Lin , Huan-Neng Chen , Kuang-Kai Yen , Ming-Chieh Liu , Tsung-Hsiung Lee
IPC分类号： G01R31/28 , H02J50/40 , H01L25/065 , H01L23/538 , H02J50/10 , H02J50/80 , G01R31/302 , H01L23/544 , G06F30/39 , H02J50/20 , H01L23/00
摘要： An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
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公开(公告)号：US20150087089A1
公开(公告)日：2015-03-26
申请号：US14561442
申请日：2014-12-05
发明人： Mill-Jer Wang , Chih-Chia Chen , Hung-Chih Lin , Ching-Nen Peng , Hao Chen
CPC分类号： G01R31/2884 , G01R1/07378 , G01R31/2834 , G01R31/2886 , H01L22/14 , Y02P80/30
摘要： A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup.
摘要翻译： 一种方法包括将具有多个探针的测试装置连接到具有多个通孔的被测器件，其中探针与被测器件的相应通孔对准，并通过导电通路进行多次通孔电特性测试 包括通孔，探针和多个导电装置，每个导电装置连接两个相邻的探针，其中导电装置处于测试装置中。
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公开(公告)号：US20140361804A1
公开(公告)日：2014-12-11
申请号：US13915409
申请日：2013-06-11
发明人： Mill-Jer Wang , Ching-Nen Peng , Hung-Chih Lin , Hao Chen , Shang-Ju Lee
IPC分类号： G01R1/073
CPC分类号： G01R31/318511 , G01R31/2889 , G01R31/318513
摘要： A system for testing a wafer includes a probe card and a wafer. The probe card includes at least one first probe site and at least one second probe site. The wafer includes a plurality of dies. The at least one first probe site is arranged for a first test, and the at least one second probe site is arranged for a second test. Each of the plurality of dies corresponds to first probe pads and second probe pads. Each of the at least one first probe site is arranged to touch the first probe pads of each of the plurality of dies. Each of the at least one second probe site is arranged to touch the second probe pads of each of the plurality of dies.
摘要翻译： 用于测试晶片的系统包括探针卡和晶片。 探针卡包括至少一个第一探针位点和至少一个第二探针位点。 晶片包括多个管芯。 所述至少一个第一探针位置被布置用于第一测试，并且所述至少一个第二探针位置被布置用于第二测试。 多个管芯中的每一个对应于第一探针焊盘和第二探针焊盘。 所述至少一个第一探针位置中的每一个被布置成接触所述多个管芯中的每一个的所述第一探针焊盘。 所述至少一个第二探针位置中的每一个被布置成接触所述多个管芯中的每一个的所述第二探针焊盘。
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公开(公告)号：US20140266281A1
公开(公告)日：2014-09-18
申请号：US13830525
申请日：2013-03-14
发明人： Mill-Jer Wang , Kuo-Chuan Liu , Ching-Nen Peng , Hung-Chih Lin , Hao Chen
IPC分类号： G01R1/04
CPC分类号： G01R31/2893 , G01R1/0483 , G01R1/06722 , G01R31/2867 , G01R31/2875 , G01R31/318513
摘要： A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.
摘要翻译： 提供了用于芯片单元的测试保持器，用于多个芯片单元的多站点保持框架和用于测试其芯片的方法。 所提出的用于同时测试多个芯片单元的多站点保持框架包括具有多个测试保持器的第一保持架。 多个测试夹具中的每一个包括一个包含多个芯片单元中的特定一个的保持器本体，以及形成在保持器主体上以当多个芯片单元中的特定一个插入保持器中时释放插入压力的压力释放装置 身体。
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公开(公告)号：US10790707B2
公开(公告)日：2020-09-29
申请号：US16220514
申请日：2018-12-14
发明人： Min-Jer Wang , Ching-Nen Peng , Chewn-Pu Jou , Feng Wei Kuo , Hao Chen , Hung-Chih Lin , Huan-Neng Chen , Kuang-Kai Yen , Ming-Chieh Liu , Tsung-Hsiung Lee
IPC分类号： G06F11/00 , G01R31/28 , H02J50/40 , H01L25/065 , H01L23/538 , H02J50/10 , H02J50/80 , G01R31/302 , H01L23/544 , G06F30/39 , H02J5/00 , H02J50/20 , H01L23/00
摘要： An integrated circuit (IC) includes a first circuit layer that includes a first wireless power transfer (WPT) device, a first chip electrically connected to the first circuit layer, and a first tracking circuit disposed in the first chip. The first WPT device may be configured to extract energy from an electromagnetic signal and provide an output voltage. The first tracking circuit may be powered by the output voltage of the first WPT device and may output tracking data in response to an instruction extracted from the electromagnetic signal.
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