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公开(公告)号：US11269368B2
公开(公告)日：2022-03-08
申请号：US14182810
申请日：2014-02-18
摘要： A voltage reference includes a flipped gate transistor configured to receive a first current. The voltage reference further includes a first transistor configured to receive a second current, the first transistor having a first leakage current, wherein the first transistor is connected with the flipped gate transistor in a Vgs subtractive arrangement. The voltage reference further includes an output node configured to output a reference voltage, the output node connected to the first transistor. The voltage reference further includes a second transistor connected to the output node, the second transistor having a second leakage current, wherein the first leakage current is substantially equal to the second leakage current.
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2.发明授权公开(公告)号：US10381259B2
公开(公告)日：2019-08-13
申请号：US15614030
申请日：2017-06-05
发明人： Alex Kalnitsky , Chih-Wen Yao , Jun Cai , Ruey-Hsin Liu , Hsiao-Chin Tuan
IPC分类号： H01L21/265 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L21/8234 , H01L29/10
摘要： A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a portion of the substrate underneath the removed portion of the isolation feature to form a trench in the substrate, and forming a trapping feature around a bottom portion of the trench. A first sidewall and a second sidewall of the trench are in direct contact with the isolation feature, and a bottom surface of the trench is below a bottom surface of the isolation feature.
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3.发明申请公开(公告)号：US20140035158A1
公开(公告)日：2014-02-06
申请号：US13773224
申请日：2013-02-21
发明人： Kuei-Sung Chang , Chun-Wen Cheng , Alex Kalnitsky , Chia-Hua Chu
CPC分类号： H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/64 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/80 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/08145 , H01L2224/13022 , H01L2224/13124 , H01L2224/13147 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24145 , H01L2224/80896 , H01L2224/81 , H01L2224/821 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01322 , H01L2924/1205 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/00 , H01L2224/82 , H05K3/4661 , H01L2224/05552 , H01L2224/8203 , H01L2224/80001
摘要： The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.
摘要翻译： 本公开提供了堆叠半导体器件的一个实施例。 叠层半导体器件包括第一衬底; 第一衬底上的第一接合焊盘; 包括在其上制造的第二电气装置的第二基板; 在所述第二基板上方的所述第二电气装置上的第二接合焊盘，所述第二接合焊盘电连接到所述第二电气装置; 所述第二接合焊盘上的第二绝缘层具有顶表面，所述第二绝缘层朝向所述第一基板的所述第一接合焊盘接合; 以及从第一接合焊盘相反的表面穿过第一基板延伸并穿过第二绝缘层的顶表面延伸到第二接合焊盘的贯通基板通孔（“TSV”）。
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公开(公告)号：US09735266B2
公开(公告)日：2017-08-15
申请号：US13921308
申请日：2013-06-19
发明人： Alex Kalnitsky , Hsiao-Chin Tuan , Kuo-Ming Wu , Wei Tsung Huang
IPC分类号： H01L29/66 , H01L29/78 , H01L29/08 , H01L21/265 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/45 , H01L29/49
CPC分类号： H01L29/7827 , H01L21/26586 , H01L29/0869 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/4238 , H01L29/456 , H01L29/4941 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A trench metal oxide semiconductor field effect transistor (MOSFET) includes an epitaxial layer over a substrate a first trench in the epitaxial layer and a second trench in the epitaxial layer. A depth of the first trench is different from a depth of the second trench. The trench MOSFET further includes a source region surrounding the self-aligned source contact, wherein the source region is convex-shaped. The trench MOSFET further includes a self-aligned source contact between the first trench and the second trench; wherein the self-aligned source contact is connected to the source region.
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5.发明授权Systems and methods for an integrated bio-entity manipulation and processing semiconductor device 有权用于集成生物实体操纵和处理半导体器件的系统和方法公开(公告)号：US09254487B2
公开(公告)日：2016-02-09
申请号：US14310440
申请日：2014-06-20
发明人： Yi-Hsien Chang , Chun-Ren Cheng , Alex Kalnitsky , Chun-Wen Cheng
IPC分类号： G01N27/447 , G01N27/453 , B01L3/00 , B81C1/00 , G01N33/543 , H01L21/02
CPC分类号： B01L3/502792 , B01L3/502707 , B01L2400/0427 , B81B2201/0214 , B81C1/00523 , G01N33/54366 , H01L21/02
摘要： An integrated semiconductor device for manipulating and processing bio-entity samples is disclosed. The device includes a microfluidic channel that is coupled to fluidic control circuitry, a photosensor array coupled to sensor control circuitry, an optical component aligned with the photosensor array to manipulate a light signal before the light signal reaches the photosensor array, and a microfluidic grid coupled to the microfluidic channel and providing for transport of bio-entity sample droplets by electrowetting. The device further includes logic circuitry coupled to the fluidic control circuitry and the sensor control circuitry, with the fluidic control circuitry, the sensor control circuitry, and the logic circuitry being formed on a first substrate.
摘要翻译： 公开了一种用于操纵和处理生物实体样本的集成半导体器件。 该装置包括耦合到流体控制电路的微流体通道，耦合到传感器控制电路的光电传感器阵列，与光传感器阵列对准的光学部件以在光信号到达光电传感器阵列之前操纵光信号;以及耦合 涉及微流体通道并且通过电润湿提供生物实体样品液滴的输送。 该装置还包括耦合到流体控制电路和传感器控制电路的逻辑电路，流体控制电路，传感器控制电路和逻辑电路形成在第一基板上。
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6.发明授权公开(公告)号：US08895360B2
公开(公告)日：2014-11-25
申请号：US13773224
申请日：2013-02-21
发明人： Kuei-Sung Chang , Chun-Wen Cheng , Alex Kalnitsky , Chia-Hua Chu
IPC分类号： H01L23/48 , H01L25/065 , H01L23/00
CPC分类号： H01L24/09 , H01L21/76898 , H01L23/481 , H01L23/64 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/80 , H01L24/81 , H01L24/82 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L25/16 , H01L25/50 , H01L2224/0401 , H01L2224/05548 , H01L2224/05567 , H01L2224/08145 , H01L2224/13022 , H01L2224/13124 , H01L2224/13147 , H01L2224/24011 , H01L2224/24051 , H01L2224/24105 , H01L2224/24145 , H01L2224/80896 , H01L2224/81 , H01L2224/821 , H01L2224/9202 , H01L2224/9212 , H01L2225/06513 , H01L2225/06541 , H01L2225/06544 , H01L2225/06565 , H01L2924/00014 , H01L2924/01322 , H01L2924/1205 , H01L2924/1305 , H01L2924/13091 , H01L2924/15787 , H01L2924/00 , H01L2224/82 , H05K3/4661 , H01L2224/05552 , H01L2224/8203 , H01L2224/80001
摘要： The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad.
摘要翻译： 本公开提供了堆叠半导体器件的一个实施例。 叠层半导体器件包括第一衬底; 第一衬底上的第一接合焊盘; 第二基板，包括在其上制造的第二电气装置; 在所述第二基板上方的所述第二电气装置上的第二接合焊盘，所述第二接合焊盘电连接到所述第二电气装置; 所述第二接合焊盘上的第二绝缘层具有顶表面，所述第二绝缘层朝向所述第一基板的所述第一接合焊盘接合; 以及从第一接合焊盘相反的表面穿过第一基板延伸并穿过第二绝缘层的顶表面延伸到第二接合焊盘的贯通基板通孔（“TSV”）。
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公开(公告)号：US12038773B2
公开(公告)日：2024-07-16
申请号：US17370733
申请日：2021-07-08
摘要： A voltage reference includes a first current source and a flipped gate transistor coupled in series between an operating voltage node and a negative supply voltage node, a first transistor and a second current source coupled in series between the operating voltage node and the negative supply voltage node, and an output node between the first transistor and the second current source. A gate of the first transistor is coupled to a gate of the flipped gate transistor, the output node is configured to output a reference voltage, the first current source is configured to provide a first current to the flipped gate transistor, the second current source is configured to provide a second current to the first transistor, the second current being less than the first current, and the first transistor has a size greater than a size of the flipped gate transistor.
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8.发明授权Micro-electro mechanical system (MEMS) structures and methods of forming the same 有权微机电系统（MEMS）结构及其形成方法公开(公告)号：US09266714B2
公开(公告)日：2016-02-23
申请号：US14253224
申请日：2014-04-15
发明人： Chia-Pao Shu , Chia-Ming Hung , Wen-Chuan Tai , Hung-Sen Wang , Hsiang-Fu Chen , Alex Kalnitsky
CPC分类号： B81B7/0032 , B81B7/0038 , B81C1/00261 , H01L2924/0002 , H01L2924/00
摘要： A device includes a first substrate bonded with a second substrate structure. The second substrate structure includes an outgasing prevention structure. At least one micro-electro mechanical system (MEMS) device is disposed over the outgasing prevention structure.
摘要翻译： 一种器件包括与第二衬底结构接合的第一衬底。 第二基板结构包括防止结构。 至少一个微机电系统（MEMS）装置设置在防止外壳结构上。
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9.发明申请公开(公告)号：US20140299472A1
公开(公告)日：2014-10-09
申请号：US14310440
申请日：2014-06-20
发明人： Yi-Hsien Chang , Chun-Ren Cheng , Alex Kalnitsky , Chun-Wen Cheng
CPC分类号： B01L3/502792 , B01L3/502707 , B01L2400/0427 , B81B2201/0214 , B81C1/00523 , G01N33/54366 , H01L21/02
摘要： An integrated semiconductor device for manipulating and processing bio-entity samples is disclosed. The device includes a microfluidic channel that is coupled to fluidic control circuitry, a photosensor array coupled to sensor control circuitry, an optical component aligned with the photosensor array to manipulate a light signal before the light signal reaches the photosensor array, and a microfluidic grid coupled to the microfluidic channel and providing for transport of bio-entity sample droplets by electrowetting. The device further includes logic circuitry coupled to the fluidic control circuitry and the sensor control circuitry, with the fluidic control circuitry, the sensor control circuitry, and the logic circuitry being formed on a first substrate.
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公开(公告)号：US11068007B2
公开(公告)日：2021-07-20
申请号：US16177001
申请日：2018-10-31
摘要： A voltage reference includes a flipped gate transistor coupled between a first node configured to carry an operating voltage and a second node configured to carry a negative supply voltage. A first transistor and a second transistor are coupled in series between the first node and the second node, a gate of the first transistor is coupled with a gate of the flipped gate transistor, and a gate of the second transistor is configured to receive the negative supply voltage. An output node between the first transistor and the second transistor is configured to output a reference voltage, and a current source coupled between the output node and the second node is configured to supply a current through the first transistor based on a current through the flipped gate transistor.
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