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15 条记录 (耗时 0.037 秒)

    Video window control apparatus and method thereof
    3.
    发明授权
    Video window control apparatus and method thereof 失效
    视窗控制装置及其方法

    公开(公告)号：US6069669A

    公开(公告)日：2000-05-30

    申请号：US770199

    申请日：1996-12-19

    申请人： Jong-Hoon Park ,  Jin-Sang Choi ,  Seon-Ja Kim ,  Kyeong-Yeol Yu ,  Dae-Hwan Hwang

    发明人： Jong-Hoon Park ,  Jin-Sang Choi ,  Seon-Ja Kim ,  Kyeong-Yeol Yu ,  Dae-Hwan Hwang

    IPC分类号： G06F3/14 ,  G09G5/14 ,  G09G5/395 ,  H04N5/445 ,  H04N5/45 ,  H04N9/74 ,  H04N9/76 ,  H04N9/268

    CPC分类号： H04N5/45 ,  G09G5/14 ,  H04N21/4316 ,  H04N5/44591 ,  G09G2340/125 ,  G09G5/395

    摘要： An improved video window control apparatus and a method thereof which are capable of generating a plurality of video windows on a television or a computer monitor, controlling the size and position thereof, and providing a video window overlap function and a picture-in-picture function. The apparatus includes a video window flow control means for controlling the size based on an input control of a video window and a position and overlap of the video windows based on a video output control and for outputting a video windows input control signal, a video output control signal, and a video selection signal, a plurality of video memory means for receiving a video signal outputted from an external video input and processing means in accordance with the video input control signal and for limitedly outputting the video signals in accordance with a video output control signal, and a video combining means for combining the video signals from the video memory into one video signal in accordance with the video selection signal and for outputting the video signal to an external video output means.

    摘要翻译： 一种改进的视频窗口控制装置及其方法，其能够在电视或计算机监视器上产生多个视频窗口，控制其尺寸和位置，以及提供视频窗口重叠功能和画中画功能 。 该装置包括：视频窗口流控制装置，用于基于视频输出控制基于视频窗口的输入控制和视频窗口的位置和重叠来控制大小，并用于输出视频窗口输入控制信号，视频输出 控制信号和视频选择信号，多个视频存储装置，用于根据视频输入控制信号接收从外部视频输入端输出的视频信号和处理装置，并且根据视频输出限制输出视频信号 控制信号和视频组合装置，用于根据视频选择信号将来自视频存储器的视频信号组合成一个视频信号，并将视频信号输出到外部视频输出装置。

    Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter
    4.
    发明授权
    Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter 有权

    公开(公告)号：US06597622B2

    公开(公告)日：2003-07-22

    申请号：US10046174

    申请日：2002-01-16

    申请人： Joo-Sang Lee ,  Jong-Hoon Park

    发明人： Joo-Sang Lee ,  Jong-Hoon Park

    IPC分类号： G11C800

    CPC分类号： G11C8/12

    摘要： A multi-bank semiconductor memory device includes a multi-bank memory; a voltage generator having one standby driving circuit and a plurality of active driving circuits and supplying a power source voltage required for a semiconductor device; and, an up/down counter for counting a low access signal and a low precharge signal and outputting a multi-bit driving enable signal for driving the plurality of active driving circuits differentially in performing an interleaving operation. When a plurality of banks are accessed, the number of banks being currently accessed is counted by using the low access signal and the low precharge signal. The number of the voltage driving circuits is increased and decreased according to the count value.

    Hybrid memory device
    5.
    发明授权
    Hybrid memory device 有权
    混合存储设备

    公开(公告)号：US6128218A

    公开(公告)日：2000-10-03

    申请号：US377163

    申请日：1999-08-19

    申请人： Min-Young You ,  Jong-Hoon Park

    发明人： Min-Young You ,  Jong-Hoon Park

    IPC分类号： G11C11/41 ,  G11C11/00 ,  G11C16/04 ,  G11C17/00 ,  H01L27/10

    CPC分类号： G11C11/005

    摘要： A hybrid memory device according to the present invention has a RAM cell and a ROM cell that separately operate, and is capable of loading data in the ROM cell to the RAM cell. In such a hybrid memory device, to transfer the data in the ROM cell to common bit lines, transistors are respectively provided between the bit lines and the ROM cell. Accordingly, even when loading the data in the ROM cell to the RAM cell, the RAM and ROM cells can be separately operated.

    摘要翻译： 根据本发明的混合存储器件具有单独操作的RAM单元和ROM单元，并且能够将ROM单元中的数据加载到RAM单元。 在这种混合存储装置中，为了将ROM单元中的数据传送到公共位线，在位线和ROM单元之间分别设置晶体管。 因此，即使将ROM单元中的数据加载到RAM单元，也可以分别操作RAM和ROM单元。

    Charge pump device for semiconductor memory
    6.
    发明授权
    Charge pump device for semiconductor memory 有权
    用于半导体存储器的电荷泵装置

    公开(公告)号：US06765428B2

    公开(公告)日：2004-07-20

    申请号：US10028686

    申请日：2001-12-28

    申请人： Sun Min Kim ,  Jong-Hoon Park

    发明人： Sun Min Kim ,  Jong-Hoon Park

    IPC分类号： H03K301

    CPC分类号： H02M3/073 ,  H02M2001/0032 ,  H02M2003/077 ,  Y02B70/16

    摘要： A charge pump device for supplying a boosted voltage to a memory device includes a charge pump part constructed with first to nth unit charge pumps, and a multi-level detector for detecting a level of a boosted voltage to selectively drive the unit charge pumps in accordance with an amount of power consumption of the host and thereby outputting at least one level detection signal.

    摘要翻译： 用于将升压电压提供给存储器件的电荷泵装置包括由第一至第n单位电荷泵构成的电荷泵部分，以及用于检测升压电压的电平以便按照按顺序驱动单元电荷泵的多电平检测器 具有主机的功耗量，从而输出至少一个电平检测信号。

    Semiconductor memory device for reducing parasitic resistance of the I/O lines
    7.
    发明授权
    Semiconductor memory device for reducing parasitic resistance of the I/O lines 有权
    用于减小I / O线的寄生电阻的半导体存储器件

    公开(公告)号：US06314038B1

    公开(公告)日：2001-11-06

    申请号：US09754119

    申请日：2001-01-05

    申请人： Jae-Woon Kim ,  Jong-Hoon Park

    发明人： Jae-Woon Kim ,  Jong-Hoon Park

    IPC分类号： G11C700

    CPC分类号： G11C7/106 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069 ,  G11C7/18

    摘要： A semiconductor memory includes a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells outputs a first data signal through an I/O line; an I/O line driving circuit for generating a second data signal by amplifying the first data signal, wherein the I/O line driving circuit is connected to the I/O lines; a data bus driving circuit connected to the I/O line driving circuit to generate a third data signal by amplifying the second data signal; a data bus precharge circuit; and a data bus connecting the data bus driving circuit to the data bus precharge circuit, wherein the data bus precharge circuit precharges the data bus to a predetermined voltage level before the third data signal is generated and transfers a voltage of the data bus to high or low level in accordance with a logic value of the third data signal when the third data signal is generated.

    摘要翻译： 半导体存储器包括存储单元阵列，其包括多个存储单元，其中多个存储单元中的每一个通过I / O线输出第一数据信号; I / O线驱动电路，用于通过放大第一数据信号来产生第二数据信号，其中I / O线驱动电路连接到I / O线; 连接到I / O线驱动电路的数据总线驱动电路，通过放大第二数据信号产生第三数据信号; 数据总线预充电电路; 以及将数据总线驱动电路连接到数据总线预充电电路的数据总线，其中，数据总线预充电电路在产生第三数据信号之前将数据总线预充电到预定的电压电平，并将数据总线的电压传送到高或 当产生第三数据信号时，根据第三数据信号的逻辑值的低电平。

    Input buffer circuit for a semiconductor memory
    8.
    发明授权
    Input buffer circuit for a semiconductor memory 失效
    用于半导体存储器的输入缓冲电路

    公开(公告)号：US5654664A

    公开(公告)日：1997-08-05

    申请号：US623083

    申请日：1996-03-28

    申请人： Jong-Hoon Park ,  Jae-Woon Kim

    发明人： Jong-Hoon Park ,  Jae-Woon Kim

    IPC分类号： G11C11/417 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0948 ,  H01J19/82

    CPC分类号： H03K19/0027

    摘要： An input buffer circuit of a semiconductor memory capable of controlling a logic threshold voltage of the circuit according to a change in an external supply voltage, which includes an external supply voltage detecting unit for dividing the external supply voltage into a plurality of regions by comparing a plurality of voltages, which have been divided by different ratios of the entire external supply voltage, with a standard voltage; and a converting unit including a pull-up circuit and a pull-down circuit, for converting input signals of TTL level into signals of CMOS level, according to the regions of the external supply voltage obtained by the external supply voltage detecting unit. The input buffer has an advantage in that margins for a logical high input range and logical low input range are improved when converting voltages of TTL level into voltages of CMOS level, by controlling the logic threshold voltage so as to lower the logic threshold voltage when the external supply voltage level is high and raise the logic threshold voltage when the external supply voltage level is low.

    摘要翻译： 一种半导体存储器的输入缓冲电路，其能够根据外部电源电压的变化来控制电路的逻辑阈值电压，该外部电源电压包括外部电源电压检测单元，用于将外部电源电压分为多个区域， 已经将整个外部电源电压的不同比例除以多个电压与标准电压; 以及包括上拉电路和下拉电路的转换单元，用于根据由外部电源电压检测单元获得的外部电源电压的区域将TTL电平的输入信号转换成CMOS电平的信号。 输入缓冲器的优点在于，当通过控制逻辑阈值电压将TTL电平的电压转换成CMOS电平的电压来改善逻辑高输入范围和逻辑低输入范围的裕度，从而当逻辑门限电压 外部电源电压高，外部电源电压低时提高逻辑门限电压。

    PRODUCTION METHOD OF CYST EXPRESSED TRANSGENIC ANIMAL USING PKD2 GENE
    9.
    发明申请
    PRODUCTION METHOD OF CYST EXPRESSED TRANSGENIC ANIMAL USING PKD2 GENE 审中-公开
    使用PKD2基因的CYST表达转基因动物的生产方法

    公开(公告)号：US20100281553A1

    公开(公告)日：2010-11-04

    申请号：US11814723

    申请日：2006-11-03

    申请人： Jong-Hoon Park ,  Han-Woong Lee ,  Ji-Yeon Noh ,  Moon-Hee Yang ,  Yong-Hoon Sung ,  Tae-Young Lee

    发明人： Jong-Hoon Park ,  Han-Woong Lee ,  Ji-Yeon Noh ,  Moon-Hee Yang ,  Yong-Hoon Sung ,  Tae-Young Lee

    IPC分类号： A01K67/027 ,  C12N15/63

    CPC分类号： A01K67/0275 ,  A01K2217/05 ,  A01K2227/105 ,  A01K2267/035 ,  C07K14/47 ,  C12N15/8509

    摘要： Disclosed herein is a method for producing a cyst-expressed transgenic animal using a PDK2 gene. The production method comprises preparing a PKD2 protein expression vector, inserting the expression vector into the nucleus of a fertilized egg to produce a PKD2 expression vector-containing fertilized egg, and transplanting the produced fertilized egg into the uterus of a surrogate mother. According to the invention disclosed herein, there is provided a method for producing transgenic animals, in which cysts are expressed only by the overexpression of the PKD2 gene. Also, transgenic mice are provided which can be effectively used in the investigation of cyst expression mechanisms and cyst control systems.

    摘要翻译： 本文公开了使用PDK2基因产生囊肿表达的转基因动物的方法。 制备方法包括制备PKD2蛋白表达载体，将表达载体插入受精卵的细胞核中以产生含有PKD2表达载体的受精卵，并将产生的受精卵移植到代孕母亲的子宫中。 根据本文公开的发明，提供了一种生产转基因动物的方法，其中囊肿仅通过PKD2基因的过表达来表达。 此外，提供可以有效地用于调查囊肿表达机制和囊肿控制系统的转基因小鼠。

    Voltage level detecting circuit
    10.
    发明授权
    Voltage level detecting circuit 失效
    电压电平检测电路

    公开(公告)号：US5923069A

    公开(公告)日：1999-07-13

    申请号：US891098

    申请日：1997-07-10

    申请人： Jong-Hoon Park ,  Jae-Woon Kim

    发明人： Jong-Hoon Park ,  Jae-Woon Kim

    IPC分类号： G01R19/00 ,  G11C11/417 ,  H03K5/08 ,  H03K19/0175 ,  H01L29/76

    CPC分类号： H03K5/08

    摘要： An improved voltage level detecting circuit that provides stable voltage detection. The voltage level detecting circuit senses a level of a voltage to be detected only when two clock signals are at a low level after ORing the signals. After detecting the voltage level, the circuit reduces power consumption by preventing a current path between the voltage and ground. Consistent operation of the voltage level detecting circuit is achieved despite fluctuation of the voltage level to be detected caused by noise through detecting the level of the voltage only when a specific clock signal is enabled.

    摘要翻译： 提供稳定电压检测的改进的电压电平检测电路。 电压电平检测电路仅在两个时钟信号在对信号进行或运算之后处于低电平时才感测到要检测的电压电平。 在检测到电压电平后，电路通过防止电压和地之间的电流路径来降低功耗。 尽管通过仅在特定的时钟信号被使能时通过检测电压的电平来实现由噪声引起的待检测的电压电平的波动来实现电压电平检测电路的一致的操作。