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    Sample assembly for thermoelectric analyzer
    2.
    发明授权
    Sample assembly for thermoelectric analyzer 有权
    热电分析仪样品组装

    公开(公告)号：US06791335B2

    公开(公告)日：2004-09-14

    申请号：US09941879

    申请日：2001-08-29

    申请人： Taisei Hirayama ,  Masanobu Inami ,  Shuichi Matsuo ,  Koichiro Ito ,  Ryo Hattori ,  Yoshitugu Yamamoto ,  Yoshihiro Notani ,  Shinichi Miyakuni

    发明人： Taisei Hirayama ,  Masanobu Inami ,  Shuichi Matsuo ,  Koichiro Ito ,  Ryo Hattori ,  Yoshitugu Yamamoto ,  Yoshihiro Notani ,  Shinichi Miyakuni

    IPC分类号： G01N2500

    CPC分类号： G01N25/486

    摘要： In a sample assembly for a thermoelectric analyzer, typically TSC (Thermally Stimulated Current) analyzer, a sample is fixed to an electrically-insulating substrate via an adhesive layer. The material of the adhesive layer is indium or gold-tin alloy. The substrate has a pair of junction electrode layers formed thereon and a pair of electrode layers formed on the same plane of the sample. One of the electrode layers is connected with one of the junction electrode layers by electrically-conductive wire, while the other of the electrode layers is connected with the other of the junction electrode layers by another electrically-conductive wire. The substrate is made of preferably made of a highly electrically-insulating and highly thermally-conductive material which may be, for example, aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO) or aluminum oxide (Al2O3). The sample may preferably be a compound semiconductor such as GaAs.

    摘要翻译： 在用于热电分析仪的样品组件（通常为TSC（热刺激电流））分析仪中，样品通过粘合剂层固定到电绝缘基底上。 粘合剂层的材料是铟或金 - 锡合金。 基板具有形成在其上的一对接电极层和形成在样品的同一平面上的一对电极层。 一个电极层通过导电线与一个接合电极层连接，而另一个电极层通过另一个导电线与另一个接合电极层连接。 基板由优选由高电绝缘性和高导热性材料制成，其可以是例如氮化铝（AlN），氮化硼（BN），氧化铍（BeO）或氧化铝（Al 2 O 3）。 样品可优选为化合物半导体，例如GaAs。

    Compound semiconductor bipolar transistor
    3.
    发明授权
    Compound semiconductor bipolar transistor 失效
    复合半导体双极晶体管

    公开(公告)号：US5726468A

    公开(公告)日：1998-03-10

    申请号：US614688

    申请日：1996-03-13

    申请人： Tomoki Oku ,  Hirofumi Nakano ,  Shinichi Miyakuni ,  Teruyuki Shimura ,  Ryo Hattori

    发明人： Tomoki Oku ,  Hirofumi Nakano ,  Shinichi Miyakuni ,  Teruyuki Shimura ,  Ryo Hattori

    IPC分类号： H01L29/41 ,  H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/331 ,  H01L23/52 ,  H01L29/205 ,  H01L29/423 ,  H01L29/43 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/0328 ,  H01L31/0336

    CPC分类号： H01L29/7371 ,  H01L29/42304

    摘要： A semiconductor device includes a semiconductor substrate; a first active layer disposed on the semiconductor substrate; a second active layer disposed on the first active layer; a first electrode including a lower stage disposed on the second active layer and an upper stage disposed on the lower stage and having an overhanging portion protruding from the lower stage; an insulating film continuously covering a surface of the second active layer, a side surface of the lower stage of the first electrode, and a lower surface and a side surface of the overhanging portion of the upper stage; and a second electrode disposed on the surface of the first active layer at opposite sides of the second active layer, self-aligned with the second active layer. The distance between the second electrode and the second active layer is minimized and the thickness of the second electrode can be about 7000 .ANG., minimizing the resistance of the first active layer and improving high frequency characteristics. Electrical separation between the first and second active layers can be achieved reliably. Recombination at the surface of the second active layer is suppressed.

    摘要翻译： 半导体器件包括半导体衬底; 设置在所述半导体衬底上的第一有源层; 设置在所述第一有源层上的第二有源层; 第一电极，其包括设置在第二有源层上的下层和设置在下层上的上层，具有从下层突出的突出部; 绝缘膜，连续地覆盖第二有源层的表面，第一电极的下层的侧表面，以及上层的突出部的下表面和侧表面; 以及第二电极，其设置在所述第二有源层的与所述第二有源层自对准的所述第二有源层的相对侧的所述表面上。 第二电极和第二有源层之间的距离被最小化，并且第二电极的厚度可以是约7000，使第一有源层的电阻最小化并提高高频特性。 可以可靠地实现第一和第二有源层之间的电气分离。 第二活性层的表面的重组被抑制。

    Method of fabricating semiconductor device
    5.
    发明授权
    Method of fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US5888859A

    公开(公告)日：1999-03-30

    申请号：US748912

    申请日：1996-11-15

    申请人： Tomoki Oku ,  Shinichi Miyakuni ,  Nobuyuki Kasai ,  Yasutaka Kohno, deceased

    发明人： Tomoki Oku ,  Shinichi Miyakuni ,  Nobuyuki Kasai ,  Yasutaka Kohno, deceased

    IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/331 ,  H01L21/338 ,  H01L29/08 ,  H01L29/205 ,  H01L29/423 ,  H01L29/43 ,  H01L29/47 ,  H01L29/73 ,  H01L29/737 ,  H01L29/812

    CPC分类号： H01L29/66863 ,  H01L21/28587 ,  H01L21/32139 ,  H01L29/0891 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/66878 ,  H01L29/8128

    摘要： A method of making a semiconductor device includes forming a recess in a compound semiconductor substrate using a patterned insulating film on a surface of the substrate, implanting dopant ions at the bottom of the recess to form a channel region, and depositing a refractory metal film. The refractory metal film is etched, using a resist pattern, to form a gate electrode and additional dopant ions are implanted to form relatively highly doped regions intersecting the channel region. Very highly doped regions are formed my implantation, after removing the insulating film, using the gate electrode and remainder of the resist mask as an implantation mask. After stripping the resist, annealing to activate the implanted ions, and depositing a passivating film on the substrate and gate electrode, source and drain electrodes are formed. The field effect transistor thus produced has a high breakdown voltage, improved reliability, a highly controlled pinch-off voltage, and improved transconductance and operating speed.

    摘要翻译： 制造半导体器件的方法包括：在衬底的表面上使用图案化的绝缘膜在化合物半导体衬底中形成凹陷，在凹部的底部注入掺杂离子以形成沟道区，并沉积难熔金属膜。 使用抗蚀剂图案蚀刻难熔金属膜以形成栅电极，并且注入另外的掺杂剂离子以形成与沟道区相交的相对高掺杂的区域。 在去除绝缘膜之后，使用栅电极和抗蚀剂掩模的其余部分作为注入掩模，形成非常高掺杂的区域。 在剥离抗蚀剂之后，退火以激活注入的离子，并且在衬底和栅电极，源电极和漏极上形成钝化膜。 这样产生的场效应晶体管具有高的击穿电压，改进的可靠性，高度控制的截止电压以及改进的跨导和操作速度。

    Etching method for indium series compound semiconductors
    7.
    发明授权
    Etching method for indium series compound semiconductors 失效
    铟系列化合物半导体的蚀刻方法

    公开(公告)号：US5512331A

    公开(公告)日：1996-04-30

    申请号：US283819

    申请日：1994-08-01

    申请人： Shinichi Miyakuni

    发明人： Shinichi Miyakuni

    IPC分类号： G01R33/64 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  B44C1/22

    CPC分类号： H01L21/02019 ,  H01L21/30621

    摘要： An etching method for an In series compound semiconductor includes etching in a plasma etching of a flowing mixture of a halogen and nitrogen, the flow ratio of halogen to nitrogen being lower than 1, and at a gas pressure below 0.5 mTorr. An etching method for an In series compound semiconductor includes etching in a plasma etching apparatus and a mixture of halogen/inactive gas/nitrogen gas, the flow rate ratio of halogen/(halogen+inactive gas+nitrogen gas) being lower than 0.1, the flow rate ratio of nitrogen/(halogen+inactive gas+nitrogen gas) being above 0.1, and the gas pressure being below 0.5 mTorr. Etching at low ion energy produces good surface morphology, a vertical side surface configuration having an etched concave portion, and low damage.

    摘要翻译： In系列化合物半导体的蚀刻方法包括在卤素和氮的流动混合物的等离子体蚀刻中，卤素与氮的流动比低于1，并且在低于0.5mTorr的气体压力下进行蚀刻。 In系列化合物半导体的蚀刻方法包括在等离子体蚀刻装置中进行蚀刻和卤素/惰性气体/氮气的混合，卤素/（卤素+惰性气体+氮气）的流量比低于0.1， 氮/（卤素+惰性气体+氮气）的流量比大于0.1，气体压力低于0.5mTorr。 在低离子能量下蚀刻产生良好的表面形态，具有蚀刻凹部的垂直侧面构造和低损伤。

    Heterojunction bipolar transistor and method for producing the same
    8.
    发明授权
    Heterojunction bipolar transistor and method for producing the same 失效
    异质结双极晶体管及其制造方法

    公开(公告)号：US06271098B1

    公开(公告)日：2001-08-07

    申请号：US09552694

    申请日：2000-04-19

    申请人： Shinichi Miyakuni ,  Teruyuki Shimura

    发明人： Shinichi Miyakuni ,  Teruyuki Shimura

    IPC分类号： H01L21331

    CPC分类号： H01L29/66318 ,  H01L29/0817 ,  H01L29/7371

    摘要： A heterojunction bipolar transistor is provided with a ballast resistor layer in an emitter layer which prevents the current amplification factor &bgr; from decreasing. The n-GaAs carrier supply layer having a specified carrier concentration is formed between the ballast resistor layer and the n-AlGaAs layer.

    摘要翻译： 异质结双极晶体管在发射极层中设置有镇流电阻层，防止电流放大因子β降低。具有特定载流子浓度的n-GaAs载流子供应层形成在镇流电阻层和n-AlGaAs层之间 。