公开(公告)号：US20230369049A1

公开(公告)日：2023-11-16

申请号：US18350583

申请日：2023-07-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/31058 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/32139 ,  H01L21/0273

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20240290656A1

公开(公告)日：2024-08-29

申请号：US18655989

申请日：2024-05-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20210265165A1

公开(公告)日：2021-08-26

申请号：US17316008

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US11851321B2

公开(公告)日：2023-12-26

申请号：US17188933

申请日：2021-03-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ting-Li Yang ,  Kai-Di Wu ,  Ming-Da Cheng ,  Wen-Hsiung Lu ,  Cheng Jen Lin ,  Chin Wei Kang

IPC: B81B3/00 ,  B81C1/00

CPC classification number: B81B3/0081 ,  B81C1/0069 ,  B81B2203/019 ,  B81B2203/0127 ,  B81B2203/0353 ,  B81B2207/015 ,  B81C2201/013 ,  B81C2201/0181 ,  B81C2203/032 ,  B81C2203/0735

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate comprising electronic circuitry, a support substrate having a recess, a bonding layer disposed between the circuit substrate and the support substrate, through holes passing through the circuit substrate to the recess, a first conductive layer disposed on a front side of the circuit substrate, and a second conductive layer disposed on an inner wall of the recess. The first conductive layer extends into the through holes and the second conductive layer extends into the through holes and coupled to the first conductive layer.

公开(公告)号：US11721579B2

公开(公告)日：2023-08-08

申请号：US17809957

申请日：2022-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

CPC classification number: H01L21/76885 ,  H01L21/76802 ,  H01L21/76852 ,  H01L21/76871 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L2224/0231 ,  H01L2224/0235 ,  H01L2224/0239 ,  H01L2224/02331 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20210375674A1

公开(公告)日：2021-12-02

申请号：US17085619

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Wen-Hsiung Lu ,  Chin Wei Kang ,  Yung-Han Chuang ,  Lung-Kai Mao ,  Yung-Sheng Lin

IPC: H01L21/768 ,  H01L23/00

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

公开(公告)号：US20250149485A1

公开(公告)日：2025-05-08

申请号：US19013241

申请日：2025-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/488 ,  H01L23/522

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

公开(公告)号：US11742204B2

公开(公告)日：2023-08-29

申请号：US17316008

申请日：2021-05-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Jung Hsueh ,  Chen-En Yen ,  Chin Wei Kang ,  Kai Jun Zhan ,  Wei-Hung Lin ,  Cheng Jen Lin ,  Ming-Da Cheng ,  Ching-Hui Chen ,  Mirng-Ji Lii

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0273 ,  H01L21/0332 ,  H01L21/31058 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32139

Abstract: A method includes depositing a plurality of layers on a substrate, patterning a first mask overlying the plurality of layers, and performing a first etching process on the plurality of layers using the first mask. The method also includes forming a polymer material along sidewalls of the first mask and sidewalls of the plurality of layers, and removing the polymer material. The method also includes performing a second etching process on the plurality of layers using the remaining first mask, where after the second etching process terminates a combined sidewall profile of the plurality of layers comprises a first portion and a second portion, and a first angle of the first portion and a second angle of the second portion are different to each other.

公开(公告)号：US20210288009A1

公开(公告)日：2021-09-16

申请号：US17333187

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/31

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.

公开(公告)号：US12230595B2

公开(公告)日：2025-02-18

申请号：US17333187

申请日：2021-05-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Da Cheng ,  Yung-Ching Chao ,  Chun Kai Tzeng ,  Cheng Jen Lin ,  Chin Wei Kang ,  Yu-Feng Chen ,  Mirng-Ji Lii

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522 ,  H01L23/488

Abstract: A method of forming an integrated circuit structure includes forming a patterned passivation layer over a metal pad, with a top surface of the metal pad revealed through a first opening in the patterned passivation layer, and applying a polymer layer over the patterned passivation layer. The polymer layer is substantially free from N-Methyl-2-pyrrolidone (NMP), and comprises aliphatic amide as a solvent. The method further includes performing a light-exposure process on the polymer layer, performing a development process on the polymer layer to form a second opening in the polymer layer, wherein the top surface of the metal pad is revealed to the second opening, baking the polymer, and forming a conductive region having a via portion extending into the second opening.