公开(公告)号：US12025914B2

公开(公告)日：2024-07-02

申请号：US18327785

申请日：2023-06-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Kuosheng Chuang

IPC: H01L21/00 ,  G03F7/06 ,  H01L21/033

CPC classification number: G03F7/06 ,  H01L21/0332 ,  H01L21/0337

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

公开(公告)号：US20240087953A1

公开(公告)日：2024-03-14

申请号：US18518081

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Lin ,  Sheng-Hsuan Lin ,  Chih-Wei Chang ,  You-Hua Chou

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/28518 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76855 ,  H01L21/76871 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2221/1073 ,  H01L2924/0002

Abstract: A semiconductor device and method of formation are provided. The semiconductor device comprises a silicide layer over a substrate, a metal plug in an opening defined by a dielectric layer over the substrate, a first metal layer between the metal plug and the dielectric layer and between the metal plug and the silicide layer, a second metal layer over the first metal layer, and an amorphous layer between the first metal layer and the second metal layer.

公开(公告)号：US20210272799A1

公开(公告)日：2021-09-02

申请号：US16803885

申请日：2020-02-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Kuo-Sheng Chuang

IPC: H01L21/027 ,  G03F7/06

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a hard mask layer over a substrate. The method further includes depositing a silver precursor layer over the hard mask layer. The method further includes exposing portions of the silver precursor layer to a radiation, the radiation causing a reduction of silver ions in the irradiated portions of the silver precursor layer. The method further includes removing non-irradiated portions of the silver precursor layer, resulting in a plurality of silver seed structures.

公开(公告)号：US11067898B2

公开(公告)日：2021-07-20

申请号：US16896218

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Kuo-Sheng Chuang

IPC: G03F7/20 ,  G21G4/00 ,  G01T1/16

Abstract: One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.

公开(公告)号：US20210033980A1

公开(公告)日：2021-02-04

申请号：US16896218

申请日：2020-06-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Kuo-Sheng Chuang

IPC: G03F7/20 ,  G01T1/16 ,  G21G4/00

Abstract: One of gamma ray lithography systems includes a gamma ray generator and a wafer stage. The gamma ray generator is configured to generate a substantially uniform gamma ray. The gamma ray generator includes a plurality of gamma ray sources and a rotational carrier. The rotational carrier is configured to hold the gamma ray sources and rotate along a rotational axis. The wafer stage is disposed below the gamma ray generator and configured to secure a wafer.

公开(公告)号：US10910483B2

公开(公告)日：2021-02-02

申请号：US16397880

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L27/12 ,  H01L27/092 ,  H01L21/02 ,  H01L21/223 ,  H01L21/8234 ,  H01L21/84

Abstract: A method and structure for forming a fin bottom diode includes providing a substrate having a plurality of fins extending therefrom. Each of the plurality of fins includes a substrate portion and an epitaxial layer portion over the substrate portion. A first dopant layer is formed on sidewalls of a first region of the substrate portion of each of the plurality of fins. After forming the first dopant layer, a first annealing process is performed to form a first diode region within the first region of the substrate portion. A second dopant layer is formed on sidewalls of a second region of the substrate portion of each of the plurality of fins. After forming the second dopant layer, a second annealing process is performed to form a second diode region within the second region of the substrate portion of each of the plurality of fins.

公开(公告)号：US10290716B2

公开(公告)日：2019-05-14

申请号：US15663791

申请日：2017-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Sheng Chuang ,  You-Hua Chou ,  Ming-Chi Huang

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/67 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/677 ,  H01L27/088 ,  H01L29/165 ,  H01L21/8234

Abstract: A semiconductor device has a semiconductor substrate. A silicon germanium layer is disposed on the semiconductor substrate. The silicon germanium layer has a first silicon-to-germanium ratio. A first gate structure is disposed on the silicon germanium layer, and the first gate structure includes an interfacial layer on the silicon germanium layer. The interface layer has a second silicon-to-germanium ratio substantially the same as the first silicon-to-germanium ratio of the silicon germanium layer. The first gate structure also includes a high-dielectric layer on the interfacial layer and a first gate electrode on the high-κ dielectric layer.

公开(公告)号：US10190209B2

公开(公告)日：2019-01-29

申请号：US15651639

申请日：2017-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-En Kao ,  Ming-Chin Tsai ,  You-Hua Chou ,  Chen-Chia Chiang ,  Chih-Tsung Lee ,  Ming-Shiou Kuo

IPC: C23C14/35 ,  H01J37/34

Abstract: A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics.

公开(公告)号：US20180284628A1

公开(公告)日：2018-10-04

申请号：US15471170

申请日：2017-03-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： You-Hua Chou ,  Kuo-Sheng Chuang

IPC: G03F7/20

Abstract: An apparatus for a lithography device is provided, which includes a laser-based particle eliminating component and a particle collector. The laser-based particle eliminating component includes a laser emitter and a laser absorbing member. The laser emitter is configured to emit laser beams for irradiating particles in a space near a photomask of the lithography device. The laser absorbing member is disposed opposite to the laser emitter for absorbing the laser beams. The particle collector is configured for collecting the irradiated particles.

公开(公告)号：US09607946B2

公开(公告)日：2017-03-28

申请号：US13967409

申请日：2013-08-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Min Hao Hong ,  Jian-Shin Tsai ,  Miao-Cheng Liao ,  Hsiang Hsiang Ko

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming a back-end-of-the-line metallization layer. The method is performed by forming a plurality of freestanding metal layer structures (i.e., metal layer structures not surrounded by a dielectric material) on a semiconductor substrate within an area defined by a patterned photoresist layer. A diffusion barrier layer is deposited onto the metal layer structure in a manner such that the diffusion barrier layer conforms to the top and sides of the metal layer structure. A dielectric material is formed on the surface of the substrate to fill areas between metal layer structures. The substrate is planarized to remove excess metal and dielectric material and to expose the top of the metal layer structure.