公开(公告)号：US20240379660A1

公开(公告)日：2024-11-14

申请号：US18781129

申请日：2024-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Chien Huang ,  Chi-Wen Liu ,  Horng-Huei Tseng ,  Tsung-Yu Chiang

IPC: H01L27/06 ,  H01L21/306 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

公开(公告)号：US20230361181A1

公开(公告)日：2023-11-09

申请号：US18353498

申请日：2023-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Ming Chang ,  Chi-Wen Liu ,  Cheng-Chien Li ,  Hsin-Chieh Huang

IPC: H01L29/36 ,  H01L29/167 ,  H01L29/06 ,  H01L29/78 ,  H01L21/265 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/36 ,  H01L29/167 ,  H01L29/0657 ,  H01L29/785 ,  H01L21/26506 ,  H01L21/02532 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

公开(公告)号：US11664218B2

公开(公告)日：2023-05-30

申请号：US17340275

申请日：2021-06-07

Applicant: National Taiwan University ,  Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Ting Fan ,  Pin-Shiang Chen ,  Chee Wee Liu ,  Chi-Wen Liu

IPC: H01L21/00 ,  H01L21/02 ,  H01L29/24 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/0228 ,  H01L29/24 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/78681 ,  H01L29/78696 ,  H01L21/02568

Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

公开(公告)号：US11532500B2

公开(公告)日：2022-12-20

申请号：US17085245

申请日：2020-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Lien Huang ,  Chi-Kang Liu ,  Chi-Wen Liu

IPC: H01L21/762 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/306 ,  H01L21/324

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

公开(公告)号：US11309385B2

公开(公告)日：2022-04-19

申请号：US16939726

申请日：2020-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Yi Peng ,  Hung-Li Chiang ,  Yu-Lin Yang ,  Chih Chieh Yeh ,  Yee-Chia Yeo ,  Chi-Wen Liu

IPC: H01L29/06 ,  H01L21/82 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/786 ,  H01L21/306 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L21/3065

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

公开(公告)号：US20200287041A1

公开(公告)日：2020-09-10

申请号：US16883227

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Chi-Wen Liu ,  Ying-Keung Leung

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/417 ,  H01L27/092 ,  H01L21/8238 ,  H01L27/108 ,  H01L27/12 ,  H01L27/088 ,  H01L29/06 ,  H01L29/45

Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US10326006B2

公开(公告)日：2019-06-18

申请号：US16229026

申请日：2018-12-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ming Peng ,  Chi-Wen Liu ,  Hsin-Chieh Huang ,  Yi-Ju Hsu ,  Horng-Huei Tseng

IPC: H01L21/70 ,  H01L29/66 ,  H01L29/78

Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.

公开(公告)号：US10164122B2

公开(公告)日：2018-12-25

申请号：US15884729

申请日：2018-01-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd. ,  National Taiwan University

Inventor： Shih-Yen Lin ,  Chi-Wen Liu ,  Chong-Rong Wu ,  Xiang-Rui Chang

IPC: H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24 ,  H01L29/778 ,  H01L29/267 ,  H01L29/417 ,  H01L29/16

Abstract: A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.

公开(公告)号：US09899537B2

公开(公告)日：2018-02-20

申请号：US15169451

申请日：2016-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yen Lin ,  Chi-Wen Liu ,  Chong-Rong Wu ,  Xian-Rui Chang

IPC: H01L29/76 ,  H01L29/786 ,  H01L29/24 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02568 ,  H01L21/0262 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/267 ,  H01L29/41766 ,  H01L29/66969 ,  H01L29/778 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78681 ,  H01L29/78684 ,  H01L29/78687

Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a first transition metal dichalcogenide film on a substrate; a second transition metal dichalcogenide film on the first transition metal dichalcogenide film; source and drain features formed over the second transition metal dichalcogenide film; and a first gate stack formed over the second transition metal dichalcogenide film and interposed between the source and drain feature.

公开(公告)号：US09721896B2

公开(公告)日：2017-08-01

申请号：US14992997

申请日：2016-01-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Lin ,  Chi-Wen Liu ,  Horng-Huei Tseng

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/53266

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.