公开(公告)号：US11908787B2

公开(公告)日：2024-02-20

申请号：US17676826

申请日：2022-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chuei-Tang Wang ,  Chun-Lin Lu ,  Kai-Chiang Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/66 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01Q1/22 ,  H01L23/31 ,  H01Q9/16 ,  H01Q9/04

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/16 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2924/3511

Abstract: A package structure includes a first and a second conductive feature structures, a die, an insulator, an encapsulant, an adhesive layer, and a first through via. The die is located between the first conductive feature structure and the second conductive feature structure. The die is electrically connected to the second conductive feature structure. The insulator is disposed between the die and the first conductive feature structure. The insulator has a bottom surface in physical contact with a polymer layer of the first conductive feature structure. The encapsulant is located between the first conductive feature structure and the second conductive feature structure. The encapsulant is disposed on the insulator and laterally encapsulates the die and the insulator. The adhesive layer is disposed between the die and the insulator. The first through via extends through the encapsulant to connect to the first conductive feature structure and the second conductive feature structure.

公开(公告)号：US20220181248A1

公开(公告)日：2022-06-09

申请号：US17676826

申请日：2022-02-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chuei-Tang Wang ,  Chun-Lin Lu ,  Kai-Chiang Wu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/66 ,  H01L21/56 ,  H01L21/683 ,  H01L21/48 ,  H01Q1/22 ,  H01Q9/16 ,  H01Q9/04 ,  H01L23/31

Abstract: A package structure includes a first and a second conductive feature structures, a die, an insulator, an encapsulant, an adhesive layer, and a first through via. The die is located between the first conductive feature structure and the second conductive feature structure. The die is electrically connected to the second conductive feature structure. The insulator is disposed between the die and the first conductive feature structure. The insulator has a bottom surface in physical contact with a polymer layer of the first conductive feature structure. The encapsulant is located between the first conductive feature structure and the second conductive feature structure. The encapsulant is disposed on the insulator and laterally encapsulates the die and the insulator. The adhesive layer is disposed between the die and the insulator. The first through via extends through the encapsulant to connect to the first conductive feature structure and the second conductive feature structure.

公开(公告)号：US11211339B2

公开(公告)日：2021-12-28

申请号：US16703468

申请日：2019-12-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chuei-Tang Wang ,  Vincent Chen ,  Tzu-Chun Tang ,  Chen-Hua Yu ,  Ching-Feng Yang ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Kai-Chiang Wu ,  Shou Zen Chang ,  Wei-Ting Lin ,  Chun-Lin Lu

IPC: H01L23/58 ,  H01L23/552 ,  H01L21/78 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor device includes a semiconductor die having an insulative layer and a conductive feature in the insulative layer, and a shield in contact with a lateral surface of the conductive feature. In some embodiments, the lateral surface of the conductive feature is aligned with an edge of the insulating material.

公开(公告)号：US10727082B2

公开(公告)日：2020-07-28

申请号：US14839047

申请日：2015-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shou Zen Chang ,  Chun-Lin Lu ,  Kai-Chiang Wu ,  Ching-Feng Yang ,  Vincent Chen ,  Chuei-Tang Wang ,  Yen-Ping Wang ,  Hsien-Wei Chen ,  Wei-Ting Lin

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/498 ,  H01L21/78 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L23/538

Abstract: A semiconductor device includes a semiconductor die. A dielectric material surrounds the semiconductor die to form an integrated semiconductor package. There is a contact coupling to the integrated semiconductor package and configured as a ground terminal for the semiconductor package. The semiconductor device further has an EMI (Electric Magnetic Interference) shield substantially enclosing the integrated semiconductor package, wherein the EMI shield is coupled with the contact through a path disposed in the integrated semiconductor package.

公开(公告)号：US10153240B2

公开(公告)日：2018-12-11

申请号：US15298054

申请日：2016-10-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Lin Lu ,  Hsien-Wei Chen ,  Kai-Chiang Wu ,  Hung-Jui Kuo

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/525 ,  H01L23/532

Abstract: Methods and apparatus are disclosed which reduce the stress concentration at the redistribution layers (RDLs) of a package device. A package device may comprise a seed layer above a passivation layer, covering an opening of the passivation layer, and covering and in contact with a contact pad. A RDL is formed above the passivation layer, above and in contact with the seed layer, covering the opening of the passivation layer, and electrically connected to the contact pad through the seed layer. The RDL has an end portion with a surface that is smooth without a right angle. The surface of the end portion of the RDL may have an obtuse angle, or a curved surface.

公开(公告)号：US09806045B2

公开(公告)日：2017-10-31

申请号：US14014051

申请日：2013-08-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Ming-Kai Liu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Chia-Chun Miao ,  Hao-Yi Tsai

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06051 ,  H01L2224/1134 ,  H01L2224/13012 ,  H01L2224/13026 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13551 ,  H01L2224/13562 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13611 ,  H01L2224/13616 ,  H01L2224/14051 ,  H01L2224/16058 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81416 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3512

Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.

公开(公告)号：US20170186726A1

公开(公告)日：2017-06-29

申请号：US14983333

申请日：2015-12-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tzu-Chun Tang ,  Chuei-Tang Wang ,  Chun-Lin Lu ,  Wei-Ting Chen ,  Vincent Chen ,  Shou-Zen Chang ,  Kai-Chiang Wu

IPC: H01L25/065 ,  H01L23/58 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/065 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/58 ,  H01L23/66 ,  H01L25/16 ,  H01L25/50 ,  H01L2223/6677 ,  H01L2224/18 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06555

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a first molding material disposed around the integrated circuit die, and a through-via disposed within the first molding material. A first side of a redistribution layer (RDL) is coupled to the integrated circuit die, the through-via, and the first molding material. A second molding material is over a second side of the RDL, the second side of the RDL being opposite the first side of the RDL. The packaged semiconductor device includes an antenna over the second molding material.

公开(公告)号：US09627325B2

公开(公告)日：2017-04-18

申请号：US13787630

申请日：2013-03-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Kai Liu ,  Chia-Chun Miao ,  Kai-Chiang Wu ,  Shih-Wei Liang ,  Ching-Feng Yang ,  Yen-Ping Wang ,  Chun-Lin Lu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/544 ,  H01L25/10 ,  H01L23/31

CPC classification number: H01L23/544 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L2224/10165 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An embodiment is a semiconductor device comprising a first bond pad on a first substrate, the first bond pad having a first center line through a center of the first bond pad and orthogonal to a top surface of the first substrate, and a first conductive connector on a second substrate, the first conductive connector having a second center line through a center of the first conductive connector and orthogonal to a top surface of the second substrate, the second substrate over the first substrate with the top surface of the first substrate facing the top surface of the second substrate. The semiconductor device further comprises a first alignment component adjacent the first bond pad on the first substrate, the first alignment component configured to align the first center line with the second center line.

公开(公告)号：US09576874B2

公开(公告)日：2017-02-21

申请号：US14961663

申请日：2015-12-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Feng Chen ,  Kai-Chiang Wu ,  Chun-Lin Lu ,  Hung-Jui Kuo

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/58 ,  H01L23/00 ,  H01L23/16 ,  H01L23/544 ,  H01L23/10 ,  H01L23/433 ,  H01L23/28 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L23/48 ,  H01L23/14 ,  H01L21/48 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L21/3205 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/34 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/10 ,  H01L23/147 ,  H01L23/16 ,  H01L23/28 ,  H01L23/31 ,  H01L23/3157 ,  H01L23/4334 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/544 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2021/6024 ,  H01L2223/5446 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/11318 ,  H01L2224/13026 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81139 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/2064 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA.

Abstract translation: 公开了半导体器件及其制造方法。 在一些实施例中，半导体器件包括衬底和设置在衬底上的多个接触焊盘。 接触垫可以布置在球栅阵列（BGA）中，并且可以包括多个拐角。 围绕多个拐角的每一个，例如BGA的拐角设置一个金属水坝。

公开(公告)号：US09355982B2

公开(公告)日：2016-05-31

申请号：US14063302

申请日：2013-10-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/17 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/06517 ,  H01L2224/09517 ,  H01L2224/10135 ,  H01L2224/1134 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/17517 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/014

Abstract: A semiconductor structure includes a semiconductor substrate and a pad. The pad is on a top surface of the semiconductor substrate. The semiconductor structure further includes a circuit board and a bump. The circuit board has a contact area corresponding to the pad on the top surface of the semiconductor substrate, and the bump is between the pad on the top surface of the semiconductor substrate and the contact area, wherein the contact area is a non-metallic surface.

Abstract translation: 半导体结构包括半导体衬底和衬垫。 衬垫位于半导体衬底的顶表面上。 半导体结构还包括电路板和凸块。 电路板具有与半导体衬底的顶表面上的焊盘对应的接触区域，并且凸起位于半导体衬底的顶表面上的焊盘和接触区域之间，其中接触面积是非金属表面 。