公开(公告)号：US20220173224A1

公开(公告)日：2022-06-02

申请号：US17152432

申请日：2021-01-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC Nanjing Company Limited

发明人： Han-Yu LIN ,  Fang-Wei LEE ,  Kai-Tak LAM ,  Raghunath PUTIKAM ,  Tzer-Min SHEN ,  Li-Te LIN ,  Pinyen LIN ,  Cheng-Tzu YANG ,  Tzu-Li LEE ,  Tze-Chung LIN

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234

摘要： A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.

公开(公告)号：US20240363421A1

公开(公告)日：2024-10-31

申请号：US18766104

申请日：2024-07-08

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Han-Yu LIN ,  Szu-Hua Chen ,  Kuan-Kan Hu ,  Kenichi Sano ,  Po-Cheng Wang ,  Wei-Yen Woon ,  Pinyen Lin ,  Che Chi Shih

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823418 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/6675 ,  H01L29/78618 ,  H01L29/78672 ,  H01L29/7869 ,  H01L29/78696

摘要： The present disclosure describes a semiconductor device with a rare earth metal oxide layer and a method for forming the same. The method includes forming fin structures on a substrate and forming superlattice structures on the fin structures, where each of the superlattice structures includes a first-type nanostructured layer and a second-type nanostructured layer. The method further includes forming an isolation layer between the superlattice structures, implanting a rare earth metal into a top portion of the isolation layer to form a rare earth metal oxide layer, and forming a polysilicon structure over the superlattice structures. The method further includes etching portions of the superlattice structures adjacent to the polysilicon structure to form a source/drain (S/D) opening and forming an S/D region in the S/D opening.

公开(公告)号：US20230268386A1

公开(公告)日：2023-08-24

申请号：US17678481

申请日：2022-02-23

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Han-Yu LIN ,  Che-Chi SHIH ,  Szu-Hua CHEN ,  Kuan-Da HUANG ,  Cheng-Ming LIN ,  Tze-Chung LIN ,  Li-Te LIN ,  Wei-Yen WOON ,  Pinyen LIN

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/0653 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0665 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

摘要： A device includes a first semiconductor structure, a second semiconductor structure, and an isolation structure which is disposed between the first and second semiconductor structures, and which includes a dielectric material having a dielectric constant higher than 8 and lower than 16. A method for manufacturing the device is also disclosed.

公开(公告)号：US20240097011A1

公开(公告)日：2024-03-21

申请号：US18526360

申请日：2023-12-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. ,  TSMC NANJING COMPANY LIMITED

发明人： Han-Yu LIN ,  Fang-Wei LEE ,  Kai-Tak LAM ,  Raghunath PUTIKAM ,  Tzer-Min SHEN ,  Li-Te LIN ,  Pinyen LIN ,  Cheng-Tzu YANG ,  Tzu-Li LEE ,  Tze-Chung LIN

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/823431 ,  H01L29/785 ,  H01L2029/7858

摘要： A method includes forming a fin structure over a substrate, wherein the fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked over a substrate; forming a dummy gate structure over the fin structure; removing a portion of the fin structure uncovered by the dummy gate structure; performing a selective etching process to laterally recess the first semiconductor layers, including injecting a hydrogen-containing gas from a first gas source of a processing tool to the first semiconductor layers and the second semiconductor layers; and injecting an F2 gas from a second gas source of the processing tool to the first semiconductor layers and the second semiconductor layers; forming inner spacers on opposite end surfaces of the laterally recessed first semiconductor layers of the fin structure; and replacing the dummy gate structure and the first semiconductor layers with a metal gate structure.

公开(公告)号：US20230215936A1

公开(公告)日：2023-07-06

申请号：US18182774

申请日：2023-03-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Han-Yu LIN ,  Chansyun David YANG ,  Fang-Wei LEE ,  Tze-Chung LIN ,  Li-Te LIN ,  Pinyen LIN

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786 ,  H01L29/423 ,  H01L21/8234

CPC分类号： H01L29/0673 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66553 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823418

摘要： A method for forming a semiconductor device structure is provided. The semiconductor device includes forming nanowire structures stacked over a substrate and spaced apart from one another, and forming a dielectric material surrounding the nanowire structures. The dielectric material has a first nitrogen concentration. The method also includes treating the dielectric material to form a treated portion. The treated portion of the dielectric material has a second nitrogen concentration that is greater than the first nitrogen concentration. The method also includes removing the treating portion of the dielectric material, thereby remaining an untreated portion of the dielectric material as inner spacer layers; and forming the gate stack surrounding nanowire structures and between the inner spacer layers.

公开(公告)号：US20230009745A1

公开(公告)日：2023-01-12

申请号：US17370265

申请日：2021-07-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Ming LIN ,  Han-Yu LIN ,  Wei-Yen WOON ,  Mrunal Abhijith KHADERBAD

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02

摘要： A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

公开(公告)号：US20240290854A1

公开(公告)日：2024-08-29

申请号：US18656033

申请日：2024-05-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tze-Chung LIN ,  Han-Yu LIN ,  Pinyen LIN ,  Fang-Wei LEE ,  Li-Te LIN

IPC分类号： H01L29/417 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L29/41775 ,  H01L21/3065 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/78696

摘要： The present disclosure describes a method includes forming a fin structure including a fin bottom portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer and a second semiconductor layer, in which the first semiconductor layer includes germanium. The method further includes etching the fin structure to form an opening, delivering a primary etchant and a germanium-containing gas to the fin structure through the opening, and etching a portion of the second semiconductor layer in the opening with the primary etchant and the germanium-containing gas.

公开(公告)号：US20240234549A1

公开(公告)日：2024-07-11

申请号：US18616449

申请日：2024-03-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Han-Yu LIN ,  Chansyun David YANG ,  Fang-Wei LEE ,  Tze-Chung LIN ,  Li-Te LIN ,  Pinyen LIN

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/321 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/6681 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/32105 ,  H01L21/3211 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

摘要： A semiconductor device structure is provided. The semiconductor device structure includes forming semiconductor device structure includes a gate stack wrapping around a plurality of nanowire structures. The gate stack includes a first portion above the plurality of nanowire structures and second portions between the nanowire structures. The semiconductor device structure further includes a gate spacer layer along a sidewall of the first portion of the gate stack, and a plurality of inner spacer layers along sidewalls of the second portions of the gate stack. The gate spacer layer has a first carbon concentration, the inner spacer layers have a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

公开(公告)号：US20220336635A1

公开(公告)日：2022-10-20

申请号：US17854615

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tze-Chung LIN ,  Han-Yu LIN ,  Li-Te LIN ,  Pinyen LIN

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/423

摘要： A method for forming a semiconductor device structure is provided. The method includes forming first semiconductor layers and second semiconductor layers on a substrate, and the first semiconductor layers and the second semiconductor layers are alternately stacked. The method includes forming a dummy gate structure over the first semiconductor layers and the second semiconductor layers, and removing a portion of the first semiconductor layers and second semiconductor layers to form a S/D trench. The method also includes removing the second semiconductor layers to form a recess connected to the S/D trench. The method includes forming a dummy dielectric layer in the recess after the dummy gate structure is formed, and the dummy dielectric layer is exposed by the S/D trench. The method includes removing a portion of the dummy dielectric layer to form a cavity and forming an inner spacer layer in the cavity.