公开(公告)号：US5556585A

公开(公告)日：1996-09-17

申请号：US361710

申请日：1994-12-22

申请人： Shinsuke Yano ,  Hirofumi Yamaguchi ,  Takami Hirai

发明人： Shinsuke Yano ,  Hirofumi Yamaguchi ,  Takami Hirai

IPC分类号： C04B35/195 ,  H01B3/08 ,  H01B3/12 ,  H05K1/03

CPC分类号： H05K1/0306 ,  C04B35/195 ,  H01B3/085 ,  H01B3/12 ,  Y10S428/901

摘要： A dielectric ceramic body prepared by firing a mixture of a cordierite glass powder and a TiO.sub.2 powder, or a mixture of these powders and a RE.sub.2 Ti.sub.2 O.sub.7 powder (RE representing a rare earth element), wherein particles of the TiO.sub.2 powder or particles of the TiO.sub.2 powder and the RE.sub.2 Ti.sub.2 O.sub.7 powder are dispersed in a matrix phase of crystalline cordierite produced from the fired cordierite glass powder. In the first case, the cordierite glass powder and the TiO.sub.2 powder have a proportion which satisfies 70.ltoreq.x

摘要翻译： 通过煅烧堇青石玻璃粉末和TiO 2粉末的混合物或这些粉末和RE 2 Ti 2 O 7粉末（代表稀土元素的RE）的混合物制备的介电陶瓷体，其中TiO 2粉末或TiO 2粉末的颗粒 并将RE2Ti2O7粉末分散在由烧制的堇青石玻璃粉末制成的结晶堇青石的基质相中。 在第一种情况下，堇青石玻璃粉末和TiO 2粉末具有满足70

公开(公告)号：US20130049202A1

公开(公告)日：2013-02-28

申请号：US13331253

申请日：2011-12-20

申请人： Makoto TANI ,  Takami Hirai ,  Shinsuke Yano ,  Daishi Tanabe

发明人： Makoto TANI ,  Takami Hirai ,  Shinsuke Yano ,  Daishi Tanabe

IPC分类号： H01L23/48 ,  H05K1/09 ,  H05K1/00

CPC分类号： H05K3/4629 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5283 ,  H01L2924/0002 ,  H05K1/0242 ,  H05K3/4623 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09827 ,  H01L2924/00

摘要： In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit hoard with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.

摘要翻译： 在根据本发明的层压和烧结陶瓷电路板中，面内导体的至少一部分被精细地排列，使得细衬面内导体的横截面的形状是梯形，并且高度 （a）中，梯形截面的下基部的长度（c）和上基部的长度（d）以及梯形截面的梯形截面的下基座之间的间隔（b） 在与板的主表面平行的平面中相邻的面内导体满足一定关系。 这提供了在小型和短路（薄）半导体封装中具有低开路故障率，短路故障率和高温和高湿度的高可靠性的层压陶瓷电路板。

公开(公告)号：US20120019334A1

公开(公告)日：2012-01-26

申请号：US13115396

申请日：2011-05-25

申请人： Takami HIRAI ,  Masahiko Namerikawa ,  Shinsuke Yano

发明人： Takami HIRAI ,  Masahiko Namerikawa ,  Shinsuke Yano

IPC分类号： H03H7/38

CPC分类号： H03H7/38 ,  H01F17/02 ,  H01F2017/0026

摘要： The present invention intends to provide a small-sized impedance matching device with a small variation in quality and large-current tolerance. The above described intention of the present invention is achieved by an impedance matching device, which comprises a wiring portion comprising a conductor pattern for wiring, embedded inside or formed on the surface of first dielectric material, and either one or both of an inductor portion comprising a conductor pattern for inductor, embedded inside or formed on the surface of the first dielectric material, or a capacitor portion comprising at least one pair of conductor patterns for capacitor and second dielectric material with a dielectric constant larger than that of the first dielectric material, existing between the pair of conductor patterns for capacitor wherein the thicknesses of the conductor pattern for wiring and the conductor pattern for inductor are 20 μm or more.

摘要翻译： 本发明旨在提供一种具有小质量变化和大电流公差的小型阻抗匹配装置。 本发明的上述目的是通过一种阻抗匹配装置来实现的，阻抗匹配装置包括一个布线部分，该布线部分包括嵌入或形成在第一介电材料的表面上的用于布线的导体图案，以及电感器部分中的一个或两个，包括 用于电感器的导体图案，嵌入或形成在第一电介质材料的表面上，或电容器部分，其包括用于电容器的至少一对导体图案和介电常数大于第一介电材料的介电常数的第二介电材料， 存在于用于电容器的一对导体图案之间，其中用于布线的导体图案的厚度和电感器的导体图案的厚度为20μm以上。

公开(公告)号：US08558640B2

公开(公告)日：2013-10-15

申请号：US12968758

申请日：2010-12-15

申请人： Takami Hirai ,  Shinsuke Yano ,  Takanobu Saka

发明人： Takami Hirai ,  Shinsuke Yano ,  Takanobu Saka

IPC分类号： H01P5/18 ,  H01P3/08

CPC分类号： H01P5/185

摘要： A directional coupler includes a dielectric substrate having at least an input terminal and an output terminal on a surface thereof, a main line disposed in the dielectric substrate and extending between the input terminal and the output terminal, a first coupling line for monitoring a level of an input signal which is input through the input terminal, the first coupling line being disposed in the dielectric substrate and having an end electrically connected to a first terminating resistor, and a second coupling line for monitoring a level of a reflected signal which is input through the output terminal, the second coupling line being disposed in the dielectric substrate and having an end electrically connected to a second terminating resistor.

摘要翻译： 定向耦合器包括：电介质基板，其至少具有输入端和在其表面上的输出端，设置在电介质基板中并在输入端和输出端之间延伸的主线;第一耦合线，用于监测电平 输入信号，其通过输入端输入，第一耦合线设置在电介质基片中，并具有电连接到第一终端电阻的端，以及第二耦合线，用于监测反射信号的电平， 所述输出端子，所述第二耦合线设置在所述电介质基板中，并且具有与第二终端电阻器电连接的端部。

公开(公告)号：US5448209A

公开(公告)日：1995-09-05

申请号：US219533

申请日：1994-03-29

申请人： Takami Hirai ,  Tatsumi Sugiura ,  Shinsuke Yano

发明人： Takami Hirai ,  Tatsumi Sugiura ,  Shinsuke Yano

IPC分类号： H01P1/203 ,  H01P1/205 ,  H01P7/08

CPC分类号： H01P1/20345

摘要： A laminated dielectric filter has a plurality of resonant elements disposed on a dielectric layer which constitute quarter-wave stripline resonators, respectively. The resonant elements have ends connected to a ground electrode. The dielectric layer also supports a plurality of electrodes having ends connected to the ground electrode and opposite ends spaced from and confronting respective open ends of the resonant elements. The laminated dielectric filter has another dielectric layer which supports thereon an electrode positioned in overlapping relationship to the resonant elements. Still another dielectric layer supports an input electrode positioned in overlapping relationship to the resonant elements and the electrode on the other dielectric layer and an output electrode positioned in overlapping relationship to the resonant elements and the electrode on the other dielectric layer. The laminated dielectric filter provides an attenuation pole to improve attenuation characteristics, suffers less variation of frequency at the pole, and can easily be reduced in size.

摘要翻译： 层压介质滤波器具有分别构成四分之一波段带状线谐振器的电介质层上的多个谐振元件。 谐振元件具有连接到接地电极的端部。 电介质层还支撑多个电极，其端部连接到接地电极，并且相对端与谐振元件的相应开口端间隔开并面对。 叠层介质滤波器具有另一个电介质层，其在其上支撑着与谐振元件重叠的位置的电极。 另一个电介质层支持与谐振元件和另一电介质层上的电极重叠的输入电极和与谐振元件和另一个电介质层上的电极重叠的位置的输出电极。 层压介质滤波器提供衰减极以改善衰减特性，在极点处频率变化较小，并且可以容易地减小尺寸。

公开(公告)号：US5412358A

公开(公告)日：1995-05-02

申请号：US24303

申请日：1993-03-01

申请人： Takami Hirai ,  Shinsuke Yano

发明人： Takami Hirai ,  Shinsuke Yano

IPC分类号： H01P1/203

CPC分类号： H01P1/20336 ,  H01P1/20363 ,  H01P1/20381

摘要： A transmission line filter having an improved attenuation characteristic is disclosed. The transmission line filter includes at least input-side and output-side resonators disposed in a dielectric layer which are inductively coupled with each other. Additionally, intermediate resonators may be disposed between the input-side and output-side resonators. Further, input and output electrodes are provided in another dielectric layer, at least one of which is in an opposed facing relationship to a portion of the input-side resonator and a portion of the output-side resonator, so as to overlap only those portions of the input-side and output-side resonators. Where intermediate resonators are disposed, at least one of the input and output electrodes is disposed in an opposed facing relationship to one of the input-side and output-side resonators and a respective adjacent intermediate resonator so as overlap only the above-noted input-side resonator or output-side resonator and respective adjacent intermediate resonator.

摘要翻译： 公开了具有改进的衰减特性的传输线滤波器。 传输线滤波器至少包括设置在彼此感应耦合的电介质层中的输入侧和输出侧谐振器。 此外，中间谐振器可以设置在输入侧和输出侧谐振器之间。 此外，输入电极和输出电极设置在另一个电介质层中，其中至少一个电介质层与输入侧谐振器的一部分和输出侧谐振器的一部分处于相对的对置关系，以仅与那些部分重叠 的输入侧和输出侧谐振器。 在设置中间谐振器的地方，输入和输出电极中的至少一个以与输入侧和输出侧谐振器之一相对的相对的关系和相邻的相邻的中间谐振器的方式设置， 侧谐振器或输出侧谐振器和相应的相邻中间谐振器。

公开(公告)号：US5185304A

公开(公告)日：1993-02-09

申请号：US745180

申请日：1991-08-15

申请人： Takami Hirai ,  Shinsuke Yano ,  Masahiro Abe

发明人： Takami Hirai ,  Shinsuke Yano ,  Masahiro Abe

IPC分类号： C04B35/468 ,  H01B3/12

CPC分类号： C04B35/4686 ,  H01B3/12

摘要： A dielectric ceramic composition is disclosed which consists principally of barium oxide, titanium oxide, neodymium oxide, samarium oxide and bismuth oxide, which are represented by the following formula xBaO--yTiO.sub.2 --z[(1-a-b)Nd.sub.2 O.sub.3 --aSm.sub.2 O.sub.3 --bBi.sub.2 O.sub.3 ], where 0.10.ltoreq.x.ltoreq.0.20, 0.60.ltoreq.y.ltoreq.0.75, 0.10.ltoreq.z.ltoreq.0.24, x+y+z=1, 0

公开(公告)号：US08847681B2

公开(公告)日：2014-09-30

申请号：US12909226

申请日：2010-10-21

申请人： Masahiko Namerikawa ,  Shinsuke Yano ,  Yasufumi Horio ,  Tatsuya Tsuruoka ,  Takami Hirai ,  Hideaki Okubo ,  Atsuo Mizuma

发明人： Masahiko Namerikawa ,  Shinsuke Yano ,  Yasufumi Horio ,  Tatsuya Tsuruoka ,  Takami Hirai ,  Hideaki Okubo ,  Atsuo Mizuma

IPC分类号： H03F1/02 ,  H01P5/18 ,  H01P5/12 ,  H03F3/60

CPC分类号： H03F1/0288 ,  H01P5/12 ,  H01P5/187 ,  H03F3/602 ,  H03F2200/204

摘要： A combiner for a Doherty amplifier includes, on and in a dielectric substrate, a carrier input terminal, a peak input terminal, an output terminal, a combining point for combining an output signal from the carrier amplifier and an output signal from the peak amplifier, a first λ/4 line connected between the carrier input terminal and the combining point, a second λ/4 line connected between the combining point and the output terminal, and a first directional coupler. The first directional coupler includes a third λ/4 line electromagnetically coupled to one, to be monitored, of the first λ/4 line and the second λ/4 line.

摘要翻译： Doherty放大器的组合器在电介质衬底上和电介质衬底中包括载波输入端，峰值输入端，输出端，用于组合来自载波放大器的输出信号和来自峰值放大器的输出信号的组合点， 连接在载波输入端和组合点之间的第一λ/ 4线，连接在组合点和输出端之间的第二λ/ 4线和第一定向耦合器。 第一定向耦合器包括电磁耦合到第一λ/ 4线和第二λ/ 4线的待监视的第三λ/ 4线。

公开(公告)号：US08487439B2

公开(公告)日：2013-07-16

申请号：US13237259

申请日：2011-09-20

申请人： Makoto Tani ,  Takami Hirai ,  Shinsuke Yano ,  Tsutomu Nanataki

发明人： Makoto Tani ,  Takami Hirai ,  Shinsuke Yano ,  Tsutomu Nanataki

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/40

CPC分类号： H01L23/49822 ,  H01L23/15 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4629 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

摘要： A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.

摘要翻译： 提供了可以降低与温度变化相关联地在半导体元件和板之间作用的热应力并且具有作为整个板（包括多层布线层）的高机械强度（刚性）的电路板。 具有与半导体元件和内层布线接近的热膨胀系数的陶瓷基材一体烧结，并且电路板被构造成使得与内层布线中的多层布线层相对应的细线导体结构具有预定的 宽度，内膜间隔和层间间隔。 因此，抑制了在与半导体元件接合的状态下板暴露于温度变化时半导体元件与基板之间的热应力，保持板的刚性，并且提高其对温度循环的可靠性。

公开(公告)号：US08421215B2

公开(公告)日：2013-04-16

申请号：US13331253

申请日：2011-12-20

申请人： Makoto Tani ,  Takami Hirai ,  Shinsuke Yano ,  Daishi Tanabe

发明人： Makoto Tani ,  Takami Hirai ,  Shinsuke Yano ,  Daishi Tanabe

IPC分类号： H01L23/12 ,  H01L23/053 ,  H01L23/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/00

CPC分类号： H05K3/4629 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5283 ,  H01L2924/0002 ,  H05K1/0242 ,  H05K3/4623 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/098 ,  H05K2201/09827 ,  H01L2924/00

摘要： In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.

摘要翻译： 在根据本发明的层压和烧结陶瓷电路板中，面内导体的至少一部分被精细地排列，使得细衬面内导体的横截面的形状是梯形，并且高度 （a）中，梯形截面的下基部的长度（c）和上基部的长度（d）以及梯形截面的梯形截面的下基座之间的间隔（b） 在与板的主表面平行的平面中相邻的面内导体满足一定关系。 这提供了在小型化和短路（薄）半导体封装中具有低开路故障率，短路故障率和高温和高湿度的高可靠性的层压陶瓷电路板。