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公开(公告)号：US06740564B2
公开(公告)日：2004-05-25
申请号：US10192629
申请日：2002-07-11
IPC分类号： H01L23544
CPC分类号： H01L21/76847 , H01L21/76849 , H01L21/76877
摘要： A method for manufacturing a semiconductor device wherein a contact hole formed in an interlayer insulating film on a semiconductor substrate is filled with a plug for electrically connecting an overlying conductor layer with an underlying conductor layer. The plug fills the contact hole, and comprised a tungsten film the upper end whereof is positioned below the upper surface of the interlayer insulating film, and a tungsten film which is filled on the tungsten film in the contact hole and the upper surface whereof is on substantially the same level as the upper surface of the interlayer insulating film.
摘要翻译： 一种制造半导体器件的方法，其中形成在半导体衬底上的层间绝缘膜中的接触孔填充有用于将上覆导体层与下面的导体层电连接的插头。 插头填充接触孔，并且包括其上端位于层间绝缘膜的上表面下方的钨膜，以及填充在接触孔中的钨膜上的钨膜和其上表面 与层间绝缘膜的上表面基本相同的水平。
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公开(公告)号：US06503836B2
公开(公告)日：2003-01-07
申请号：US09782281
申请日：2001-02-14
IPC分类号： H01L21302
CPC分类号： H01L21/31053 , H01L21/31625 , H01L21/76825 , H01L21/76828
摘要： A method and apparatus for manufacturing a semiconductor device having an interlayer insulating film of improved flatness after a CMP process are obtained. The method includes the steps of: heat-treating a semiconductor device having an interlayer insulating film containing impurities; conducting a process for making an impurity-concentration distribution at an upper layer portion of the interlayer insulating film substantially uniform after the heat treatment; and polishing the interlayer insulating film by a CMP process after the process for making the impurity-concentration distribution substantially uniform.
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公开(公告)号：US06573603B2
公开(公告)日：2003-06-03
申请号：US09865501
申请日：2001-05-29
IPC分类号： H01L2348
CPC分类号： H01L21/76804 , H01L21/76832
摘要： There are described a semiconductor device having multilayer wiring and a method for manufacturing the semiconductor device, wherein an interconnection hole for interconnecting an upper wiring layer to a lower wiring layer is formed correctly, thereby improving the reliability of multilayer wiring. A lower silicon oxide film, an upper silicon oxide film, and a silicon nitride film to be interposed therebetween are formed on a spin-on-glass (SOG) film. Enlarged openings for interconnection holes are formed only within the upper silicon oxide film while the silicon nitride film is used as an etch stopper, thereby preventing extension of the enlarged openings to the SOG film.
摘要翻译： 描述了具有多层布线的半导体器件和用于制造半导体器件的方法，其中正确地形成用于将上布线层与下布线层互连的互连孔，从而提高多层布线的可靠性。 在旋涂玻璃（SOG）膜上形成要置于其间的较低氧化硅膜，上氧化硅膜和氮化硅膜。 用于互连孔的扩大开口仅在上氧化硅膜内形成，而氮化硅膜用作蚀刻停止层，从而防止扩大的开口延伸到SOG膜。
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公开(公告)号：US08350322B2
公开(公告)日：2013-01-08
申请号：US12885395
申请日：2010-09-17
申请人： Takeru Matsuoka
发明人： Takeru Matsuoka
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： According to one embodiment, a semiconductor device includes a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a source region of the first conductivity type, a first and a second main electrode, trench gates, a first and a second contact region. The third semiconductor layer is provided on the second semiconductor layer provided on the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is electrically connected to the source region provided on the third semiconductor layer. The trench gates are provided from the third semiconductor layer to the second semiconductor layer. The first and second contact regions electrically connect the second main electrode and the third semiconductor layer. An opening area of the second contact hole is smaller than that of the first contact hole.
摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一和第二半导体层，第二导电类型的第三半导体层，第一导电类型的源极区，第一和第二主电极，沟槽 门，第一和第二接触区域。 第三半导体层设置在设置在第一半导体层上的第二半导体层上。 第一主电极电连接到第一半导体层。 第二主电极电连接到设置在第三半导体层上的源极区域。 沟槽栅极从第三半导体层提供到第二半导体层。 第一和第二接触区域电连接第二主电极和第三半导体层。 第二接触孔的开口面积小于第一接触孔的开口面积。
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5.发明授权公开(公告)号：US06888258B2
公开(公告)日：2005-05-03
申请号：US10603811
申请日：2003-06-26
申请人： Takeru Matsuoka , Noriaki Fujiki , Hiroki Takewaka
发明人： Takeru Matsuoka , Noriaki Fujiki , Hiroki Takewaka
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L23/485 , H01L23/532 , H01L23/48 , H01L29/40
CPC分类号： H01L24/05 , H01L23/53219 , H01L23/53228 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05073 , H01L2224/05147 , H01L2224/05166 , H01L2224/05187 , H01L2224/05546 , H01L2224/05556 , H01L2224/05624 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2224/48799 , H01L2224/48824 , H01L2924/00011 , H01L2924/04941 , H01L2924/00014 , H01L2924/01014 , H01L2924/01029 , H01L2924/04953 , H01L2924/00 , H01L2924/00015 , H01L2924/01005 , H01L2924/01004
摘要： A contact and a copper interconnect line as an uppermost interconnect layer are buried in an interlayer insulating film. A pad area including aluminum alloy (such as AlCu or AlSiCu) is buried in a predetermined area of the copper interconnect line. A gold wire is bonded to the pad area.
摘要翻译： 作为最上层的互连层的接触和铜互连线被埋在层间绝缘膜中。 包括铝合金（例如AlCu或AlSiCu）的焊盘区域被埋在铜互连线的预定区域中。 金线结合到焊盘区域。
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公开(公告)号：US06586838B2
公开(公告)日：2003-07-01
申请号：US09909781
申请日：2001-07-23
申请人： Noriaki Fujiki , Takeru Matsuoka , Hiroki Takewaka
发明人： Noriaki Fujiki , Takeru Matsuoka , Hiroki Takewaka
IPC分类号： H01L2348
CPC分类号： H01L23/53295 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： To provide excellent reliability and high yield of a semiconductor device that has a multi-wiring structure by using a fluorine-containing silicon oxide film as an interlayer insulating film. A fluorine-containing silicon oxide film is formed so as to cover a lower layer metal wiring. A TEOS film is formed on the fluorine-containing silicon oxide film. After planarizing the TEOS film with the CMP method, an SiH4-based silicon oxide film that is suitable for capturing fluorine is formed on the TEOS film. Metal wirings are formed on the SiH4-based silicon oxide film. A predetermined heat treatment is performed to capture fluorine inside the SiH4-based silicon oxide film. The SiH4-based silicon oxide film is patterned to the same pattern as the metal wirings. After diffusing fluorine into the atmosphere from the exposed area of the TEOS film, a silicon nitride film is formed on the metal wirings.
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公开(公告)号：US06417575B2
公开(公告)日：2002-07-09
申请号：US09726599
申请日：2000-12-01
申请人： Shigeru Harada , Takeru Matsuoka , Hiroki Takewaka
发明人： Shigeru Harada , Takeru Matsuoka , Hiroki Takewaka
IPC分类号： H01L2348
CPC分类号： H01L24/05 , H01L21/76807 , H01L24/03 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05093 , H01L2224/05546 , H01L2224/05552 , H01L2224/05555 , H01L2224/05647 , H01L2224/13099 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48463 , H01L2224/48647 , H01L2224/48847 , H01L2224/85201 , H01L2224/85205 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01029 , H01L2924/01047 , H01L2924/0105 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/13091 , H01L2924/181 , H01L2924/19043 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device includes a pad electrode and a main electrode layer of the pad electrode has a plan view shape of one selected from the group consisting of a near circle, a near ellipse, a near polygon with at least one internal angle larger than 90 degrees and a near polygon with at least one corner chamfered or rounded. The main electrode layer is connected to a lower electrode layer beneath the man electrode layer via a connection hole interposed therebetween and a lower protruding section is provided beneath the lower electrode layer. A stress buffer insulating partition and a stress buffer protruding section are more preferably provided at corners of the layers, connection hole and lower protruding section.
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公开(公告)号：US20110108911A1
公开(公告)日：2011-05-12
申请号：US12885395
申请日：2010-09-17
申请人： Takeru Matsuoka
发明人： Takeru Matsuoka
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/41766 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： According to one embodiment, a semiconductor device includes a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a source region of the first conductivity type, a first and a second main electrode, trench gates, a first and a second contact region. The third semiconductor layer is provided on the second semiconductor layer provided on the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is electrically connected to the source region provided on the third semiconductor layer. The trench gates are provided from the third semiconductor layer to the second semiconductor layer. The first and second contact regions electrically connect the second main electrode and the third semiconductor layer. An opening area of the second contact hole is smaller than that of the first contact hole.
摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一和第二半导体层，第二导电类型的第三半导体层，第一导电类型的源极区，第一和第二主电极，沟槽 门，第一和第二接触区域。 第三半导体层设置在设置在第一半导体层上的第二半导体层上。 第一主电极电连接到第一半导体层。 第二主电极电连接到设置在第三半导体层上的源极区域。 沟槽栅极从第三半导体层提供到第二半导体层。 第一和第二接触区域电连接第二主电极和第三半导体层。 第二接触孔的开口面积小于第一接触孔的开口面积。
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公开(公告)号：US06683000B2
公开(公告)日：2004-01-27
申请号：US10228307
申请日：2002-08-27
申请人： Shoichi Fukui , Takeru Matsuoka
发明人： Shoichi Fukui , Takeru Matsuoka
IPC分类号： H01L2144
CPC分类号： H01L21/76877
摘要： A semiconductor-device fabrication method includes a step of forming a contact hole in a semiconductor substrate 1 and a step of forming a conductive contact hole. The step of forming the contact hole is performed by repeating two times or more a burying step of depositing a conductive material 5 to bury the conductive material in the contact hole and an etch-back step of removing the conductive material around the contact hole by etch back.
摘要翻译： 半导体器件制造方法包括在半导体衬底1中形成接触孔的步骤和形成导电接触孔的步骤。 形成接触孔的步骤通过重复两次或更多次沉积导电材料5以将导电材料埋入接触孔中的掩埋步骤和通过蚀刻去除接触孔周围的导电材料的回蚀步骤来进行 背部。
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公开(公告)号：US06483140B1
公开(公告)日：2002-11-19
申请号：US09481387
申请日：2000-01-12
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10873 , H01L27/10888
摘要： A lower insulating film is formed so as to cover source/drain regions electrically connected to capacitors. Bit lines and upper insulating layers are formed on the lower insulating film. SCs opening to the lower insulating film are formed by an anisotropic etching process on process conditions for etching the upper insulating films at a high upper insulating film/lower insulating film selectivity. An insulating film of a quality equal to that of the lower insulating film is deposited so as to fill up the SCs and to cover the upper insulating film. The SCs is extended so as to open to the source/drain regions by an anisotropic etching process on process conditions for etching the lower insulating film at a high lower insulating film/silicon film selectivity.
摘要翻译： 形成下绝缘膜以覆盖与电容器电连接的源极/漏极区域。 位线和上绝缘层形成在下绝缘膜上。 通过各向异性蚀刻工艺，以高上绝缘膜/下绝缘膜选择性蚀刻上绝缘膜的工艺条件形成通向下绝缘膜的SC。 沉积质量等于下绝缘膜的绝缘膜，以填充SC并覆盖上绝缘膜。 通过各向异性蚀刻工艺对SCs进行扩展，以在较低的绝缘膜/硅膜选择性下蚀刻下绝缘膜的工艺条件下对源/漏区开放。
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