利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

11 条记录 (耗时 0.016 秒)

    Automatic tracking system for antenna
    1.
    发明授权
    Automatic tracking system for antenna 失效
    天线自动跟踪系统

    公开(公告)号：US4586050A

    公开(公告)日：1986-04-29

    申请号：US532606

    申请日：1983-09-15

    申请人： Takao Kuroda ,  Ryuji Shimizu

    发明人： Takao Kuroda ,  Ryuji Shimizu

    IPC分类号： H01Q1/28 ,  G01S3/44 ,  G05D1/08 ,  H01Q1/18 ,  H01Q3/02 ,  H01Q3/08 ,  G01S5/02 ,  H04B7/185

    CPC分类号： H01Q1/18 ,  G01S3/44

    摘要： An automatic tracking system for an antenna device for satellite communications and using step tracking principles is disclosed which repeatedly effects tracking at predetermined intervals so that the receive electric field from the satellite becomes maximum. When a platform loaded with an antenna device for satellite communications is caused to sway to an inclined position during an interval between sequential tracking operations, sensors senses a pitching angle and a rolling angle of the platform. The outputs of the sensors are compared with an angle previously stored as an inclination angle of the platform which existed just before interval between sequential tracking operations. If the difference is larger than a predetermined value, step tracking is resumed to track the satellite even in a suspension period of step tracking.

    摘要翻译： 公开了一种用于卫星通信的天线装置和使用步进跟踪原理的自动跟踪系统，其以预定间隔重复地进行跟踪，使得来自卫星的接收电场变得最大。 当在连续跟踪操作之间的间隔期间，装载有用于卫星通信的天线装置的平台被引导到倾斜位置时，传感器感测平台的俯仰角和滚动角度。 将传感器的输出与先前存储为在顺序跟踪操作之前存在的平台的倾斜角度的角度进行比较。 如果该差大于预定值，则即使在步进跟踪的暂停时段中，仍继续进行跟踪以跟踪卫星。

    Built-in self-test circuit
    2.
    发明授权
    Built-in self-test circuit 有权
    内置自检电路

    公开(公告)号：US07117394B2

    公开(公告)日：2006-10-03

    申请号：US10436132

    申请日：2003-05-13

    申请人： Ryuji Shimizu

    发明人： Ryuji Shimizu

    IPC分类号： G06F11/00

    CPC分类号： G11C29/38 ,  G01R31/31703 ,  G01R31/3187

    摘要： A built-in self-test (BIST) circuit is configured to divide data output bits of a RAM macro into a plurality of groups each consisting of 2 bits, and provide a 1-bit comparator of a signature analyzer for each group to share one 1-bit comparator by respective two data output bits. A selector of a bit changer sequentially selects a data output bit from each group, and the 1-bit comparator sequentially compares output data for the selected data output bit with expected value data.

    摘要翻译： 内置的自检（BIST）电路被配置为将RAM宏的数据输出位分成由2位组成的多个组，并且为每个组提供一个签名分析器的1位比较器来共享一个 1位比较器由相应的两个数据输出位组成。 比特变换器的选择器顺序地选择每个组的数据输出位，并且1位比较器顺序地将所选数据输出位的输出数据与期望值数据进行比较。

    Delay failure test circuit
    3.
    发明申请
    Delay failure test circuit 失效
    延时故障测试电路

    公开(公告)号：US20070288184A1

    公开(公告)日：2007-12-13

    申请号：US11717769

    申请日：2007-03-14

    申请人： Hideaki Konishi ,  Ryuji Shimizu ,  Masayasu Hojo ,  Haruhiko Abe ,  Satoshi Masuda ,  Naofumi Kobayashi

    发明人： Hideaki Konishi ,  Ryuji Shimizu ,  Masayasu Hojo ,  Haruhiko Abe ,  Satoshi Masuda ,  Naofumi Kobayashi

    IPC分类号： G01R29/02

    CPC分类号： G01R31/31858 ,  G01R31/318552 ,  G01R31/318594

    摘要： In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

    摘要翻译： 在延迟故障测试电路中，执行具有不同操作时钟速率的多个时钟域中的两个时钟域之间的延迟失败测试。 延迟故障测试电路向第一时钟域输入仅具有用于将数据从第一时钟域传送到第二时钟域的发射边缘的时钟信号，并将仅具有唯一的时钟信号输入到第二时钟域 用于捕获数据的捕获边。

    RAM functional test facilitation circuit with reduced scale
    4.
    发明授权
    RAM functional test facilitation circuit with reduced scale 失效
    RAM功能测试促进电路规模缩小

    公开(公告)号：US06810498B2

    公开(公告)日：2004-10-26

    申请号：US10106052

    申请日：2002-03-27

    申请人： Ryuji Shimizu

    发明人： Ryuji Shimizu

    IPC分类号： G01R328

    CPC分类号： G11C29/12 ,  G11C2029/3202

    摘要： The outputs of selectors 230 to 23N are respectively connected to the data inputs DI0 to DIN of a RAM 10A. One inputs of selectors 540 to 54N are respectively connected to the data outputs DO0 to DON of the RAM 10A, the other inputs are connected to corresponding outputs of the selectors 230 to 23N. The outputs of the selectors 540 to 54N are connected to data inputs D of respective scan flip-flops 520 to 52N. Not in a RAM test mode, data input lines 210 to 21N are selected by the selectors 230 to 23N to provide to the data inputs DI0 to DIN of the RAM 10A and to the scan flip-flops 520 to 52N through the selectors 540 to 54N, respectively.

    摘要翻译： 选择器230至23N的输出分别连接到RAM 10A的数据输入DI0至DIN。 选择器540至54N的一个输入分别连接到RAM 10A的数据输出DO0至DON，其他输入连接到选择器230至23N的相应输出。 选择器540至54N的输出连接到各扫描触发器520至52N的数据输入端D. 不是在RAM测试模式中，数据输入线210至21N由选择器230至23N选择，以通过选择器540至54N提供给RAM 10A的数据输入DI0至DIN，以及扫描触发器520至52N ， 分别。

    Antenna beam pointing method for satellite mobile communications system
    5.
    发明授权
    Antenna beam pointing method for satellite mobile communications system 失效
    用于卫星移动通信系统的天线波束点方法

    公开(公告)号：US5241319A

    公开(公告)日：1993-08-31

    申请号：US687729

    申请日：1991-04-19

    申请人： Ryuji Shimizu

    发明人： Ryuji Shimizu

    IPC分类号： G01S3/40 ,  H01Q1/27 ,  H01Q1/32 ,  H01Q3/02 ,  H01Q3/26

    CPC分类号： H01Q1/3275 ,  H01Q3/02 ,  H01Q3/2605

    摘要： A method for tracking a satellite in a land mobile satellite communications system is disclosed. A rate gyro is provided for use in the event that an automatic satellite tracking is prevented. The satellite is automatically tracked using a receive signal level if the receive signal level equals or exceeds a threshold. An output of the rate gyro is constantly compensated while automatically tracking the satellite. When the receive signal level falls below the threshold and the automatic satellite tracking becomes unable, the satellite is tracked using the compensated output of the rate gyro.

    Delay failure test circuit
    8.
    发明授权
    Delay failure test circuit 失效
    延时故障测试电路

    公开(公告)号：US07640124B2

    公开(公告)日：2009-12-29

    申请号：US11717769

    申请日：2007-03-14

    申请人： Hideaki Konishi ,  Ryuji Shimizu ,  Masayasu Hojo ,  Haruhiko Abe ,  Satoshi Masuda ,  Naofumi Kobayashi

    发明人： Hideaki Konishi ,  Ryuji Shimizu ,  Masayasu Hojo ,  Haruhiko Abe ,  Satoshi Masuda ,  Naofumi Kobayashi

    IPC分类号： G01R29/02

    CPC分类号： G01R31/31858 ,  G01R31/318552 ,  G01R31/318594

    摘要： In a delay failure test circuit, a delay failure test between two clock domains among a plurality of clock domains having different operation clock rates is performed. The delay failure test circuit inputs, to a first clock domain, a clock signal having only a launch edge for transferring data from the first clock domain to a second clock domain, and to input, to the second clock domain, a clock signal having only a capture edge for capturing the data.

    摘要翻译： 在延迟故障测试电路中，执行具有不同操作时钟速率的多个时钟域中的两个时钟域之间的延迟失败测试。 延迟故障测试电路向第一时钟域输入仅具有用于将数据从第一时钟域传送到第二时钟域的发射边缘的时钟信号，并将仅具有唯一的时钟信号输入到第二时钟域 用于捕获数据的捕获边。

    Method of and apparatus for timing verification of LSI test data and computer product
    10.
    发明授权
    Method of and apparatus for timing verification of LSI test data and computer product 失效
    LSI测试数据和计算机产品的定时验证方法和设备

    公开(公告)号：US06910166B2

    公开(公告)日：2005-06-21

    申请号：US10253713

    申请日：2002-09-25

    申请人： Masahito Suzuki ,  Ryuji Shimizu

    发明人： Masahito Suzuki ,  Ryuji Shimizu

    IPC分类号： G01R31/28 ,  G01R31/3183 ,  G06F11/263 ,  G06F17/50 ,  G06F11/00

    CPC分类号： G01R31/318357 ,  G01R31/318307 ,  G06F11/263 ,  G06F17/5031

    摘要： Timing verification of the LSI test data is performed as follows. In test synthesis, a script text for static timing analysis (STA) is generated together with a test circuit. The STA script text is used to perform static timing analysis. Function verification is performed between a netlist generated through the test synthesis and a timing-verified netlist based on the static timing analysis. The function-verified netlist is released to a production division, and the netlist is used to automatically generate a test pattern by an automatic test pattern generation (ATPG) tool. A netlist comprising test vectors for automatic test equipment is acquired from the generated ATPG pattern.

    摘要翻译： LSI测试数据的定时验证如下进行。 在测试合成中，静态时序分析（STA）的脚本文本与测试电路一起生成。 STA脚本文本用于执行静态时序分析。 在通过测试合成产生的网表和基于静态时序分析的定时验证网表之间执行功能验证。 功能验证的网表被发布到生产部门，网表用于通过自动测试模式生成（ATPG）工具自动生成测试模式。 从生成的ATPG模式中获取包含用于自动测试设备的测试向量的网表。