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55 条记录 (耗时 0.022 秒)

    Driving circuit for providing a voltage boasted over the power supply voltage source as a driving signal
    1.
    发明授权
    Driving circuit for providing a voltage boasted over the power supply voltage source as a driving signal 失效
    用于提供在电源电压源上吹过的电压作为驱动信号的驱动电路

    公开(公告)号：US5103113A

    公开(公告)日：1992-04-07

    申请号：US537554

    申请日：1990-06-13

    申请人： Takashi Inui ,  Shunichi Sukegawa

    发明人： Takashi Inui ,  Shunichi Sukegawa

    IPC分类号： G06F1/025 ,  H03K19/013

    CPC分类号： H03K19/013 ,  G06F1/025

    摘要： A driving circuit for providing a predetermined voltage as a driving signal to a respective word line in a dynamic random access memory in a short time. The driving circuit includes an operation signal supply circuit portion for providing an operation signal, a driving signal output circuit portion which receives the operation signal and provides a driving signal as an output, and a voltage supply circuit portion for providing a predetermined voltage to the driving signal output circuit portion in producing the driving signal. A bipolar switching element is provided in the driving signal output circuit portion to control the voltage supply from the voltage supply circuit portion and responds to the operation signal to provide the voltage from the voltage supply circuit portion as the voltage producing the driving signal in a short time.

    摘要翻译： 一种用于在短时间内向动态随机存取存储器中的相应字线提供预定电压作为驱动信号的驱动电路。 驱动电路包括用于提供操作信号的操作信号供给电路部分，接收操作信号并提供驱动信号作为输出的驱动信号输出电路部分和用于向驱动提供预定电压的电压供应电路部分 信号输出电路部分产生驱动信号。 双极开关元件设置在驱动信号输出电路部分中，以控制来自电压供应电路部分的电压供应，并响应于操作信号，以提供来自电压供应电路部分的电压作为短路产生驱动信号 时间。

    Semiconductor integrated circuit device
    2.
    发明授权
    Semiconductor integrated circuit device 失效
    半导体集成电路器件

    公开(公告)号：US5021852A

    公开(公告)日：1991-06-04

    申请号：US353858

    申请日：1989-05-18

    申请人： Shunichi Sukegawa ,  Takashi Inui

    发明人： Shunichi Sukegawa ,  Takashi Inui

    IPC分类号： H01L27/06 ,  H01L27/108

    CPC分类号： H01L27/10829 ,  H01L27/0623

    摘要： This invention relates to a semiconductor integrated circuit device which has an insulated-gate type element part comprising a capacitor which is formed through the use of a trench in a semiconductor layer, wherein a low-resistance buried layer is formed in the semiconductor layer prior to forming the trench so that the trench is formed to be surrounded by the low-resistance buried layer and thereby the low-resistance buried layer is used as an electrode of the capacitor.

    摘要翻译： 本发明涉及具有绝缘栅型元件的半导体集成电路器件，该绝缘栅型元件包括通过使用半导体层中的沟槽形成的电容器，其中在半导体层之前形成低电阻掩埋层 形成沟槽，使得沟槽形成为被低电阻掩埋层包围，从而将低电阻掩埋层用作电容器的电极。

    Word line driving circuit
    3.
    发明授权
    Word line driving circuit 失效
    字线驱动电路

    公开(公告)号：US5557580A

    公开(公告)日：1996-09-17

    申请号：US292452

    申请日：1994-08-18

    申请人： Shigeki Numaga ,  Shunichi Sukegawa ,  Takashi Inui ,  Yukihide Suzuki ,  Kiyoshi Nakai

    发明人： Shigeki Numaga ,  Shunichi Sukegawa ,  Takashi Inui ,  Yukihide Suzuki ,  Kiyoshi Nakai

    IPC分类号： G11C11/407 ,  G11C8/08 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

    CPC分类号： G11C8/08

    摘要： A word line driving circuit which effectively prevents ground noise during word line discharge along with accommodating the narrowing of pitch in the word lines by making the layout area of the word line driver small. The word line driving circuit includes n-type MOS transistor 14 and p-type MOS transistor 12. The drain terminal of n-type MOS transistor 14 and drain terminal of p-type MOS transistor 12 in word line driver 10 are connected to the base terminal of word line WLi. The output terminal of an output transistor driving circuit 16 is connected to the source terminal of p-type MOS transistor 12, and the output terminal of a first output transistor controlling circuit 18 is connected to the gate terminal. The output terminal of a second output transistor controlling circuit 20 is connected to the gate terminal of n-type MOS transistor 14, and a ground terminal 22 as a reference potential terminal for leading in the electric current is connected to the source terminal.

    摘要翻译： 一种字线驱动电路，通过使字线驱动器的布局面积小，能够有效地防止字线放电期间的接地噪声，同时容纳字线中的音调变窄。 字线驱动电路包括n型MOS晶体管14和p型MOS晶体管12. n型MOS晶体管14的漏极端子和字线驱动器10中的p型MOS晶体管12的漏极端子连接到基极 字线WLi的终端。 输出晶体管驱动电路16的输出端子与p型MOS晶体管12的源极端子连接，第一输出晶体管控制电路18的输出端子与栅极端子连接。 第二输出晶体管控制电路20的输出端子与n型MOS晶体管14的栅极端子连接，作为引导电流的基准电位端子的接地端子22与源极端子连接。

    Dynamic RAM
    5.
    发明授权
    Dynamic RAM 失效
    动态RAM

    公开(公告)号：US08068379B1

    公开(公告)日：2011-11-29

    申请号：US09050946

    申请日：1998-03-31

    申请人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

    发明人： Tsutomu Takahashi ,  Kouji Arai ,  Yasushi Takahashi ,  Atsuya Tanaka ,  Shunichi Sukegawa ,  Shinji Bessho ,  Masayuki Hira

    IPC分类号： G11C8/00

    CPC分类号： H01L27/0207 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/4097 ,  H01L27/10891

    摘要： A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select line arranged in parallel to the main word line is extended to a plurality of sub arrays arranged in the extension direction of the word line. A second sub word select line is connected to the corresponding one of said first sub word select line to be extended orthogonally to a word line driving circuit area of an adjacent sub array. In the sub word line driving circuit provided for each sub array, a sub word line is selected and deselected by signals supplied from said main word line and said second sub word select line.

    摘要翻译： 多个子字线各自具有与沿着其延伸方向的主字线的划分相等的长度，沿着与所述主字线交叉的位线布置，并且与多个存储单元连接。 与主字线平行布置的第一子字选择线被扩展到沿字线的延伸方向布置的多个子阵列。 第二子字选择线连接到所述第一子字选择线中的相应一个，以与正交相邻子阵列的字线驱动电路区域正交延伸。 在为每个子阵列提供的子字线驱动电路中，通过从所述主字线和所述第二子字选择线提供的信号来选择和取消副字线。

    Semiconductor memory device
    8.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07012831B2

    公开(公告)日：2006-03-14

    申请号：US10749559

    申请日：2004-01-02

    申请人： Kenichi Shigenami ,  Shunichi Sukegawa

    发明人： Kenichi Shigenami ,  Shunichi Sukegawa

    IPC分类号： G11C11/24

    CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/4076

    摘要： A semiconductor memory device for realizing high speed writing while maintaining the credibility of write data, wherein a write gate is provided between a bit line and an input/output data line of a memory cell array, the write gate becomes open when a selected word line becomes an activation state and a write signal set to the input/output data line in accordance with write data is applied to the selected bit line via the write gate when writing, so that writing of data to a selected memory cell can be performed immediately after activating the selected word line when writing, and writing to the selected memory cell can be performed in parallel with reading and refreshing of non-selected memory cells, and consequently, a time for storing charges to the selected memory cell can be sufficiently secured and writing at a high speed can be realized.

    摘要翻译： 一种用于在保持写入数据的可信度的同时实现高速写入的半导体存储器件，其中在存储单元阵列的位线和输入/输出数据线之间提供写入门，当选择的字线 成为激活状态，并且根据写数据设置到输入/输出数据线的写入信号在写入时经由写入门被施加到所选择的位线，使得可以在之后立即执行到所选择的存储器单元的写入 在写入时激活所选择的字线，并且可以与未选择的存储单元的读取和刷新并行地执行对所选择的存储器单元的写入，因此可以充分确保用于存储对所选存储单元的电荷的时间和写入 可以实现高速度。

    Semiconductor memory device having a back gate voltage controlled delay circuit
    10.
    发明授权
    Semiconductor memory device having a back gate voltage controlled delay circuit 有权
    具有背栅电压控制延迟电路的半导体存储器件

    公开(公告)号：US6034920A

    公开(公告)日：2000-03-07

    申请号：US198816

    申请日：1998-11-24

    申请人： Shunichi Sukegawa ,  Shinji Bessho ,  Tadashi Tachibana ,  Hiroyuki Yoshida

    发明人： Shunichi Sukegawa ,  Shinji Bessho ,  Tadashi Tachibana ,  Hiroyuki Yoshida

    IPC分类号： G11C7/06 ,  G11C8/18 ,  G11C8/00

    CPC分类号： G11C8/18 ,  G11C7/06

    摘要： A semiconductor memory device has an address buffer (200, 230). A pre-decoder circuit (202, 232) receives the output of the address buffer (200, 230), and a memory array (212) receives the output of the pre-decoder circuit. A main amplifier (216, 248) in turn receives the output of the memory array (212, 244). An address transition detector (ATD) pulse generator circuit (204, 234) also receives the output of the address buffer (200, 230), and a pulse delay circuit (208, 240) receives the output of the address transition detector pulse generator circuit (204, 234). The pulse delay circuit (208, 240) also provides a main amplifier signal to the main amplifier (216, 248). The memory device further includes a voltage generator (206, 236) that generates a back gate voltage which is provided as a low voltage supply (V.sub.BB) for the address transition detector (ATD) pulse generator circuit (204, 234) and the pulse delay circuit (208, 240). The address transition detector (ATD) pulse generator (204, 234) and the pulse delay circuit (208, 240) have a delay that is controlled by the back gate voltage (V.sub.BB) and has a reduced dependency on a high voltage supply (V.sub.DD) of the memory device.

    摘要翻译： 半导体存储器件具有地址缓冲器（200,230）。 预解码器电路（202,232）接收地址缓冲器（200,230）的输出，存储器阵列（212）接收预解码器电路的输出。 主放大器（216,248）又接收存储器阵列（212,244）的输出。 地址转换检测器（ATD）脉冲发生器电路（204,234）还接收地址缓冲器（200,230）的输出，并且脉冲延迟电路（208,240）接收地址转换检测器脉冲发生器电路的输出 （204,234）。 脉冲延迟电路（208,240）还向主放大器（216,248）提供主放大器信号。 存储装置还包括产生背栅电压的电压发生器（206,236），该栅极电压作为用于地址转换检测器（ATD）脉冲发生器电路（204,234）的低电压电源（VBB）和脉冲延迟 电路（208,240）。 地址转换检测器（ATD）脉冲发生器（204,234）和脉冲延迟电路（208,240）具有由背栅极电压（VBB）控制的延迟，并且对高电压源（VDD）的依赖性降低 ）的存储器件。