公开(公告)号：US08456335B2

公开(公告)日：2013-06-04

申请号：US13297505

申请日：2011-11-16

Applicant: Takashi Oshima

Inventor： Takashi Oshima

IPC: H03M1/10

CPC classification number: H03M1/1052 ,  H03M1/068 ,  H03M1/468

Abstract: In a successive approximation ADC, resolution is limited because a distortion occurs in an A/D conversion result due to a voltage dependence of a sampling capacitance. An A/D converter includes a sampling capacitor part in which capacitors equal in capacitance value to each other are connected inversely, a successive approximation A/D conversion part that conducts A/D conversion on the sampling charge, a digital correction part that corrects capacitance variation of internal DAC capacitors in the successive approximation A/D conversion part, and a digital correction part that digitally corrects a third-order or more factor of a voltage dependence of the sampling charge.

Abstract translation: 在逐次逼近ADC中，由于采样电容的电压依赖性，在A / D转换结果中发生失真，所以分辨率受到限制。 A / D转换器包括一个采样电容器部分，其中电容值彼此相等的电容相反地连接，对采样电荷进行A / D转换的逐次逼近A / D转换部分，校正电容的数字校正部分 逐次逼近A / D转换部分中的内部DAC电容器的变化，以及数字校正部分，其对数字校正采样电荷的电压依赖性的三阶或更多因子。

公开(公告)号：US08102289B2

公开(公告)日：2012-01-24

申请号：US12676357

申请日：2009-02-19

Applicant: Takashi Oshima ,  Taizo Yamawaki ,  Tomomi Takahashi

Inventor： Takashi Oshima ,  Taizo Yamawaki ,  Tomomi Takahashi

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/804

Abstract: In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. In this configuration, samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

Abstract translation: 在传统的时间交错模拟/数字转换器的数字校准技术中，不可能执行支持下一代应用的高速采样率的高精度校准，并实现高分辨率。 对于其解决方案，参考A / D转换单元并联连接到时间交织的A / D转换器的公共端作为校准目标，并且构成时间的每个单位A / D转换单元的输出 通过使用从参考A / D转换单元输出的低速高分辨率A / D转换结果，在数字区域校准交错A / D转换器。 另外，fCLK / N（fCLK表示时间交织的A / D转换器的总体采样率，N是并行连接的单位A / D转换单元的数量的N相对于M）被设定为操作时钟频率 参考A / D转换单元。 在这种配置中，所有单位A / D转换单元的采样可以与参考A / D转换单元的采样顺序同步，并且参考A / D转换器的操作时钟频率可以比总体的N倍慢 时间交织A / D转换器的采样率。

公开(公告)号：US20110128171A1

公开(公告)日：2011-06-02

申请号：US12676357

申请日：2009-02-19

Applicant: Takashi Oshima ,  Taizo Yamawaki ,  Tomomi Takahashi

Inventor： Takashi Oshima ,  Taizo Yamawaki ,  Tomomi Takahashi

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/00 ,  H03M1/0695 ,  H03M1/1028 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/804

Abstract: In the digital calibration technique of the conventional time-interleaved analog/digital converter, it is impossible to perform highly-accurate calibration that supports a high-speed sampling rate of the next-generation application and achieves a high resolution. For its solution, a reference A/D conversion unit is connected in parallel to an input common to a time-interleaved A/D converter to be a calibration target, and the output of each unitary A/D conversion unit which makes up the time-interleaved A/D converter is calibrated in a digital region by using a low-speed high-resolution A/D conversion result output from the reference A/D conversion unit. Also, fCLK/N (fCLK represents an overall sampling rate of the time-interleaved A/D converter, and N is relatively prime to the number of unitary A/D conversion units connected in parallel M) is set as the operation clock frequency of the reference A/D conversion unit. In this configuration, samplings of all unitary A/D conversion units can be sequentially synchronized with the sampling of the reference A/D conversion unit, and the operation clock frequency of the reference A/D converter can be made N times slower than the overall sampling rate of the time-interleaved A/D converter.

Abstract translation: 在传统的时间交错模拟/数字转换器的数字校准技术中，不可能执行支持下一代应用的高速采样率的高精度校准，并实现高分辨率。 对于其解决方案，参考A / D转换单元并联连接到时间交织的A / D转换器的公共端作为校准目标，并且构成时间的每个单位A / D转换单元的输出 通过使用从参考A / D转换单元输出的低速高分辨率A / D转换结果，在数字区域校准交错A / D转换器。 另外，fCLK / N（fCLK表示时间交织的A / D转换器的总体采样率，N是并行连接的单位A / D转换单元的数量的N相对于M）被设定为操作时钟频率 参考A / D转换单元。 在这种配置中，所有单一A / D转换单元的采样可以与参考A / D转换单元的采样顺序同步，并且参考A / D转换器的操作时钟频率可以比总体的N倍慢 时间交织A / D转换器的采样率。

公开(公告)号：US07898862B2

公开(公告)日：2011-03-01

申请号：US12626787

申请日：2009-11-27

Applicant: Tetsuya Murakami ,  Takashi Oshima

Inventor： Tetsuya Murakami ,  Takashi Oshima

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10

Abstract: A semiconductor device includes a transfer section which receives, from an external source, a second program for modifying a function of a first program stored in a read-only memory (ROM) and information required in activation of the second program, and which writes the program and the information to a nonvolatile semiconductor memory, and a load section which activates the second program on the basis of the information written to the nonvolatile semiconductor memory to modify the function of the first program.

Abstract translation: 半导体器件包括：传输部分，其从外部源接收用于修改存储在只读存储器（ROM）中的第一程序的功能的第二程序和激活第二程序所需的信息， 程序和信息到非易失性半导体存储器，以及负载部分，其基于写入到非易失性半导体存储器的信息来激活第二程序，以修改第一程序的功能。

公开(公告)号：US07843369B2

公开(公告)日：2010-11-30

申请号：US12270212

申请日：2008-11-13

Applicant: Tomomi Takahashi ,  Takashi Oshima ,  Taizo Yamawaki

Inventor： Tomomi Takahashi ,  Takashi Oshima ,  Taizo Yamawaki

IPC: H03M1/10

CPC classification number: H03M1/1033 ,  H03M1/12

Abstract: In a wireless transmitter and receiver, a background calibration type analog-to-digital converter generally occupies a large area because of the phase compensating capacity of an op-amp included in a reference analog-to-digital conversion unit. Further, the calibration type analog-to-digital converter generally requires a sample and hold circuit to exclude influence of parasitic capacitance of wirings, thereby increasing power consumption. Digital calibration is performed by using, as a signal for calibration, an input signal of a digital-to-analog converter in a transmitter circuit of the wireless transmitter and receiver and inputting an output signal from the digital-to-analog converter to the analog-to-digital converter in the receiver circuit.

Abstract translation: 在无线发射机和接收机中，由于参考模数转换单元中包含的运算放大器的相位补偿能力，背景校准型模拟 - 数字转换器通常占用大面积。 此外，校准型模拟 - 数字转换器通常需要采样和保持电路来排除布线的寄生电容的影响，从而增加功耗。 通过使用无线发射机和接收机的发射机电路中的数模转换器的输入信号作为校准信号，并将来自数模转换器的输出信号输入到模拟数字校准 数字转换器。

公开(公告)号：US07764216B2

公开(公告)日：2010-07-27

申请号：US12216821

申请日：2008-07-11

Applicant: Takashi Oshima ,  Taizo Yamawaki

Inventor： Takashi Oshima ,  Taizo Yamawaki

IPC: H03M1/12

CPC classification number: H03M1/1042 ,  H03M1/0673 ,  H03M1/0692 ,  H03M1/183 ,  H03M1/44 ,  H03M1/46

Abstract: In an analog-to-digital converter, when a capacitive element with a small capacitance is used in order to reduce power consumption, the characteristics of the analog-to-digital converter deteriorate due to the variation in the specific accuracy. Further, the method of reducing the variation with the specific accuracy causes an increase in the size of the circuit and power consumption. An analog-to-digital converter includes an analog core unit having at least one capacitive element. The capacitive element includes a capacitive bank having plural capacitive element units having substantially the same capacitance value, and the capacitive bank is configured to select one capacitive element unit from the plural capacitive element units with substantially equal probability.

Abstract translation: 在模数转换器中，当使用具有小电容的电容元件以降低功耗时，由于特定精度的变化，模数转换器的特性恶化。 此外，以特定精度减小变化的方法导致电路的尺寸和功耗的增加。 模数转换器包括具有至少一个电容元件的模拟核心单元。 电容元件包括具有多个具有大致相同的电容值的电容元件单元的电容库，并且该电容库被配置为以几乎相等的概率从多个电容元件单元中选择一个电容元件单元。

公开(公告)号：US07649774B2

公开(公告)日：2010-01-19

申请号：US11680978

申请日：2007-03-01

Applicant: Takashi Oshima

Inventor： Takashi Oshima

IPC: G11C11/34 ,  G11C16/04 ,  G11C8/00 ,  G06F13/00

CPC classification number: G06F13/28

Abstract: A memory unit includes a plurality of first blocks each having a first block size. Each of the first blocks stores data of a plurality of second blocks each having a second block size which is smaller than the first block size. A control unit writes the data of the second block in the first block. The control unit is configured such that in a case where the second block to be written is a block that is to be written in the same first block as the second block that is already written in the first block, the second block to be written is written in the same first block even if an address of the second block to be written is not consecutive to an address of the second block that is already written in the first block.

Abstract translation: 存储单元包括多个第一块，每个第一块具有第一块大小。 每个第一块存储多个第二块的数据，每个第二块具有小于第一块大小的第二块大小。 控制单元将第二块的数据写入第一块。 控制单元被配置为使得在要写入的第二块是要写入与已经写入第一块的第二块相同的第一块中的块的情况下，要写入的第二块是 即使要写入的第二块的地址与已经写入第一块的第二块的地址不连续，也写入相同的第一块。

公开(公告)号：US20090096540A1

公开(公告)日：2009-04-16

申请号：US12243553

申请日：2008-10-01

Applicant: Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

Inventor： Takashi Kawamoto ,  Masaru Kokubo ,  Takashi Oshima

IPC: H03L7/085

CPC classification number: H03L7/18 ,  H03K19/0027 ,  H03L7/0995 ,  H03L7/23

Abstract: A logical level converter generates an output signal by which a logical circuit accurately operates even if there is a threshold fluctuation factor. In the logical level converter, an output signal of a voltage control oscillator in a phase locked loop is inputted to a threshold variable inverter. A DC component of another output signal from the threshold variable inverter is inputted to a comparator, and compared with a comparison voltage. A threshold setting signal is outputted on the basis of a comparison result. The threshold value of the threshold variable inverter is changed according to the threshold variable signal, and the output signal is converted into the other output signal. When the comparison result comes to a given state, the value of the threshold setting signal is held, and the other output signal is outputted as a further different output signal.

Abstract translation: 逻辑电平转换器产生输出信号，由此即使存在阈值波动因子，逻辑电路也能精确地操作。 在逻辑电平转换器中，锁相环中的电压控制振荡器的输出信号被输入到阈值可变变换器。 来自阈值可变逆变器的另一输出信号的DC分量被输入到比较器，并与比较电压进行比较。 基于比较结果输出阈值设定信号。 阈值可变逆变器的阈值根据阈值可变信号而改变，并且输出信号被转换成另一个输出信号。 当比较结果达到给定状态时，保持阈值设置信号的值，并且输出另一个输出信号作为另一个不同的输出信号。

公开(公告)号：US20070208913A1

公开(公告)日：2007-09-06

申请号：US11680978

申请日：2007-03-01

Applicant: Takashi Oshima

Inventor： Takashi Oshima

IPC: G06F13/00

CPC classification number: G06F13/28

Abstract: A memory unit includes a plurality of first blocks each having a first block size. Each of the first blocks stores data of a plurality of second blocks each having a second block size which is smaller than the first block size. A control unit writes the data of the second block in the first block. The control unit is configured such that in a case where the second block to be written is a block that is to be written in the same first block as the second block that is already written in the first block, the second block to be written is written in the same first block even if an address of the second block to be written is not consecutive to an address of the second block that is already written in the first block.

Abstract translation: 存储单元包括多个第一块，每个第一块具有第一块大小。 每个第一块存储多个第二块的数据，每个第二块具有小于第一块大小的第二块大小。 控制单元将第二块的数据写入第一块。 控制单元被配置为使得在要写入的第二块是要写入与已经写入第一块的第二块相同的第一块中的块的情况下，要写入的第二块是 即使要写入的第二块的地址与已经写入第一块的第二块的地址不连续，也写入相同的第一块。

公开(公告)号：US20070005875A1

公开(公告)日：2007-01-04

申请号：US11242873

申请日：2005-10-05

Applicant: Takashi Oshima

Inventor： Takashi Oshima

IPC: G06F12/00 ,  G06F11/00

CPC classification number: G06F11/1417 ,  G11C16/20

Abstract: There is disclosed a memory having a plurality of blocks including management information, and a centralized management block in which the management information of each block is centralized, wherein a control section detects the centralized management block in the memory at a starting time, and searches for the management information from the plurality of blocks in the memory, and writes the searched management information into the centralized management block of the memory, within a restricted time set in a system in a case where the centralized management block includes an error.

Abstract translation: 公开了一种具有包括管理信息的多个块的存储器和其中每个块的管理信息被集中在其中的集中管理块，其中控制部分在起始时间检测存储器中的集中管理块，并且搜索 来自存储器中的多个块的管理信息，并且在集中管理块包括错误的情况下，在系统内设置的限制时间内将搜索到的管理信息写入到存储器的集中管理块中。