公开(公告)号：US4876223A

公开(公告)日：1989-10-24

申请号：US260300

申请日：1988-10-20

申请人： Takashi Yoda ,  Tohru Watanabe

发明人： Takashi Yoda ,  Tohru Watanabe

IPC分类号： H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768

CPC分类号： H01L21/31133 ,  H01L21/32134 ,  H01L21/7684 ,  Y10S148/051

摘要： A method of manufacturing a semiconductor device whereby a wiring material is filled within a recess of an insulating film, with the upper surface of the wiring material being uneven, a coating film being evenly deposited on the wiring material, the wiring material and the coating film being etched with tetra-methyl-guanidine having the same etching speed with respect to the wiring material and the coating film in such a manner that the upper surface of the wiring material filled within the recess is made substantially flat and substantially flush with the upper surface of the insulating film. A tetra-methyl-guanide may be used which has a higher etching speed with respect to the wiring material than the coating film. In this case, the wiring material has an indentation above the recess, and the coating film is thick above the recess and thin above the insulating film. Therefore, the wiring material within the recess is etched in such a manner that the upper surface of the wiring material within the recess is made flat and substantially flush with the upper surface of the insulating film.

公开(公告)号：US5254872A

公开(公告)日：1993-10-19

申请号：US673265

申请日：1991-03-21

申请人： Takashi Yoda ,  Tohru Watanabe ,  Katsuya Okumura

发明人： Takashi Yoda ,  Tohru Watanabe ,  Katsuya Okumura

IPC分类号： H01L23/532 ,  H01L23/48

CPC分类号： H01L23/53223 ,  H01L2924/0002

摘要： A semiconductor device having a reliable contact is disclosed. The device includes a barrier film deposited on the bottom and side wall of a contact hole opened in a insulating film at a predetermined position; a first metal film filled in the contact hole; and a second metal film of low resistance for forming an interconnection which passes above the contact hole filled in with the first metal film. An oxide film is formed by oxidation on the barrier metal film. And a method of manufacturing the semiconductor device is disclosed. The method includes the steps of: after opening a contact hole at a predetermined position in an insulating film deposited on a semiconductor substrate, forming a barrier film in the bottom and side wall of the contact hole; filling the contact hole with a first metal film while heating the semiconductor substrate at a predetermined temperature; and depositing a second metal film over the surface of the semiconductor device and patterning the second metal film to form an interconnection which passes the contact hole that has been filled in with the first metal film.

摘要翻译： 公开了具有可靠接触的半导体器件。 该装置包括沉积在预定位置处在绝缘膜上开口的接触孔的底部和侧壁上的阻挡膜; 填充在接触孔中的第一金属膜; 以及用于形成互连件的低电阻的第二金属膜，其通过填充有第一金属膜的接触孔以上。 在阻挡金属膜上通过氧化形成氧化膜。 并且公开了一种制造半导体器件的方法。 该方法包括以下步骤：在沉积在半导体衬底上的绝缘膜中的预定位置打开接触孔之后，在接触孔的底壁和侧壁中形成阻挡膜; 在第一金属膜上填充接触孔，同时在预定温度下加热半导体衬底; 以及在所述半导体器件的表面上沉积第二金属膜，并且对所述第二金属膜进行构图以形成通过已经填充有所述第一金属膜的所述接触孔的互连。

公开(公告)号：US09281693B2

公开(公告)日：2016-03-08

申请号：US13989178

申请日：2011-03-30

申请人： Tohru Watanabe ,  Yasuko Shiga ,  Katsumi Kawano ,  Shigetoshi Sameshima ,  Yoshiki Kakumoto ,  Michiki Nakano

发明人： Tohru Watanabe ,  Yasuko Shiga ,  Katsumi Kawano ,  Shigetoshi Sameshima ,  Yoshiki Kakumoto ,  Michiki Nakano

IPC分类号： G06F19/00 ,  H02J4/00 ,  H02J3/46 ,  H02J3/32 ,  H02J3/14 ,  H02J13/00 ,  H02J3/38 ,  H02J3/00

CPC分类号： H02J4/00 ,  H02J3/14 ,  H02J3/32 ,  H02J3/383 ,  H02J3/46 ,  H02J13/0006 ,  H02J2003/007 ,  Y02B70/3225 ,  Y02E10/563 ,  Y02E10/566 ,  Y02E40/72 ,  Y02E60/76 ,  Y02E70/30 ,  Y04S10/123 ,  Y04S20/222 ,  Y04S40/22

摘要： The system control apparatus for equipment for causing equipment to collaboratively operate includes: equipment profile management means for managing an equipment profile that is metadata representing the electrical properties of the equipment; control scenario management means for managing a control scenario in which is described metadata that states an operation to be fulfilled by the equipment; equipment detection means for detecting control-targeted equipment; electrical status monitoring means for monitoring an electrical status related to transfer of electrical power caused by equipment interconnections; equipment selection means for selecting equipment for use on the basis of the metadata described in the control scenario and the equipment profile; and control execution means for controlling the selected equipment.

摘要翻译： 用于使设备协同操作的设备的系统控制装置包括：用于管理设备简档的设备简档管理装置，其是表示设备的电气特性的元数据; 用于管理控制场景的控制场景管理装置，其中描述了描述由所述设备实现的操作的元数据; 用于检测控制目标设备的设备检测装置; 电气状态监视装置，用于监测与设备互连引起的电力传递相关的电气状态; 设备选择装置，用于根据控制场景和设备配置文件中描述的元数据选择要使用的设备; 以及用于控制所选设备的控制执行装置。

公开(公告)号：US20140189416A1

公开(公告)日：2014-07-03

申请号：US14237312

申请日：2011-08-26

申请人： Yoshiyuki Tajima ,  Koichiro Iijima ,  Tohru Watanabe ,  Takaharu Ishida

发明人： Yoshiyuki Tajima ,  Koichiro Iijima ,  Tohru Watanabe ,  Takaharu Ishida

IPC分类号： G06F1/10

CPC分类号： G06F9/4881 ,  G06F9/4887 ,  G06F9/5027 ,  G06F11/30 ,  G06F11/34 ,  H02J3/14 ,  H02J4/00 ,  H02J13/0079 ,  H02J2003/007 ,  H02J2003/143 ,  Y02B70/3225 ,  Y02B70/3266 ,  Y04S20/222 ,  Y04S20/242

摘要： A calculation device is provided that executes calculations within real-time restrictions. The calculation device implements a step of predicting a processing time of a calculation related to the amount and property of input data based on a prediction model; a step of adjusting the processing time by decreasing the amount of data used for the calculation or decreasing the number of iterative calculations when the processing time exceeds a time slice allocated to the calculation; a step of executes the calculation using the adjusted processing time; a step of updating, as required, the prediction model used for predicting the processing time according to the result of the calculation which is executed in a period where the calculation is not performed while implementing a change of the amount of data or the number of iterative calculations or change to an approximation.

摘要翻译： 提供了一种在实时限制内执行计算的计算设备。 计算装置实现基于预测模型来预测与输入数据的量和属性相关的计算的处理时间的步骤; 当处理时间超过分配给计算的时间片时，通过减少用于计算的数据量或减少迭代次数来调整处理时间的步骤; 使用调整后的处理时间执行计算的步骤; 根据需要更新根据在不执行计算期间执行的计算结果来预测处理时间的预测模型的步骤，同时实现数据量的改变或迭代次数 计算或更改为近似值。

公开(公告)号：US20140099150A1

公开(公告)日：2014-04-10

申请号：US14044071

申请日：2013-10-02

申请人： Kazuyoshi Matsumoto ,  Makoto Kikura ,  Kazuyoshi Kondo ,  Yuuzoh Obata ,  Norikazu Yanase ,  Yoshinori Uchino ,  Gaku Hosono ,  Tohru Watanabe ,  Toshihisa Nakamura ,  Tadashi Okano ,  Naoki Saitoh

发明人： Kazuyoshi Matsumoto ,  Makoto Kikura ,  Kazuyoshi Kondo ,  Yuuzoh Obata ,  Norikazu Yanase ,  Yoshinori Uchino ,  Gaku Hosono ,  Tohru Watanabe ,  Toshihisa Nakamura ,  Tadashi Okano ,  Naoki Saitoh

IPC分类号： B41J13/08

CPC分类号： B41J13/08 ,  G03G15/6517 ,  G03G21/1623 ,  G03G21/1695 ,  G03G2221/1684

摘要： An image forming apparatus includes an apparatus body, a sheet feeder to load a roll body including a recording medium wound around, an image forming unit to form an image on the recording medium, and a conveyance unit including a conveyance belt to convey the recording medium drawn out from the roll body so as to oppose the recording medium to the image forming unit. The sheet feeder and the conveyance unit are integrated as a sheet feed conveyance unit. The sheet feed conveyance unit is configured to load the roll body in at least the sheet feeder and be drawable from the apparatus body to a position at which the conveyance belt is visible.

摘要翻译： 图像形成装置包括装置主体，用于装载卷绕在其上的记录介质的卷体的片材进给器，用于在记录介质上形成图像的图像形成单元，以及传送单元，该传送单元包括传送带，用于传送记录介质 从卷体拉出，以便与图像形成单元相对的记录介质。 片材进给器和输送单元被整合为片材进给输送单元。 片材进给传送单元被配置为将卷体至少装载在片材进给器中，并且可以从装置本体到达传送带可见的位置。

公开(公告)号：US07755680B2

公开(公告)日：2010-07-13

申请号：US11426754

申请日：2006-06-27

申请人： Tohru Watanabe

发明人： Tohru Watanabe

IPC分类号： H04N9/64

CPC分类号： G09G3/006 ,  G06T5/005 ,  G06T5/20 ,  G06T7/0002 ,  G09G2330/10 ,  H01L27/14806 ,  H04N5/21 ,  H04N5/367 ,  H04N5/3675

摘要： A deficiency candidate detection circuit detects a deficient pixel candidate by comparing the image signal of a target pixel with the image signals of peripheral pixels, and address information of the deficient pixel candidate is stored in a position memory circuit. A deficiency determining circuit repeats the determination of a deficient pixel a number of times based on the address information stored in the position memory circuit, and determines address information of a deficient pixel from the continuity of the determination results. A deficiency registering circuit registers the determined address information in the position memory circuit. A deficiency correction circuit corrects the image signal of the deficient pixel according to the registered address information of the deficient pixel.

摘要翻译： 不足候选检测电路通过将目标像素的图像信号与周边像素的图像信号进行比较来检测缺陷像素候选，并且将不良像素候选的地址信息存储在位置存储电路中。 缺陷判定电路基于存储在位置存储电路中的地址信息重复不良像素的判定次数，根据判定结果的连续性来判定缺陷像素的地址信息。 缺陷登记电路将确定的地址信息登记在位置存储电路中。 缺陷校正电路根据缺陷像素的注册地址信息校正缺陷像素的图像信号。

公开(公告)号：US20080170153A1

公开(公告)日：2008-07-17

申请号：US12041740

申请日：2008-03-04

申请人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

发明人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

IPC分类号： H04N5/225 ,  H04N3/14

CPC分类号： H04N5/23241 ,  H04N5/335

摘要： A signal processor for reducing power consumption. The signal processor includes a signal processing circuit and a first regulator connected to the signal processing circuit. The first regulator receives an external regulated voltage from an external regulator connected to the signal processor and generates an internal regulated voltage that is in accordance with an output level of a CCD image sensor. The signal processing circuit operates with the internal regulated voltage and performs a predetermined signal processing on an image signal generated by the CCD image sensor.

摘要翻译： 用于降低功耗的信号处理器。 信号处理器包括信号处理电路和连接到信号处理电路的第一调节器。 第一调节器从连接到信号处理器的外部调节器接收外部调节电压，并产生与CCD图像传感器的输出电平相一致的内部调节电压。 信号处理电路以内部调节电压进行动作，对由CCD图像传感器生成的图像信号进行规定的信号处理。

公开(公告)号：US07110038B2

公开(公告)日：2006-09-19

申请号：US10208141

申请日：2002-07-30

申请人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

发明人： Tohru Watanabe ,  Takashi Tanimoto ,  Tatsuya Takahashi

IPC分类号： H04N5/225

CPC分类号： H04N5/23241 ,  H04N5/335

摘要： A signal processor for reducing power consumption. The signal processor includes a first regulator for generating a first regulated voltage with a power supply voltage and supplying the first regulated voltage to a signal processing circuit. A second regulator generates a second regulated voltage with the power supply voltage and supplies the second regulated voltage to an output circuit. The second regulator shifts the second regulated voltage in accordance with a change in an input level of the external device.

摘要翻译： 用于降低功耗的信号处理器。 信号处理器包括用于产生具有电源电压的第一调节电压并将第一调节电压提供给信号处理电路的第一调节器。 第二调节器产生具有电源电压的第二调节电压，并将第二调节电压提供给输出电路。 第二调节器根据外部设备的输入电平的变化来移动第二调节电压。

公开(公告)号：US07027085B2

公开(公告)日：2006-04-11

申请号：US10235246

申请日：2002-09-04

申请人： Tohru Watanabe

发明人： Tohru Watanabe

IPC分类号： H04N5/225

CPC分类号： H04N5/2355 ,  H04N5/235 ,  H04N5/33 ,  H04N5/335

摘要： An imaging apparatus that has a reduced circuit scale and efficiently operates a plurality of solid-state imaging devices. The imaging apparatus includes first and second solid-state imaging devices, first and second drive circuits for driving the first and second solid-state imaging devices, and a timing control circuit for determining the vertical and horizontal scan timing of the first and second solid-state imaging devices in accordance with a reference clock signal having a fixed cycle. A selection circuit selects either one of the first and second image signals in synchronism with an operation timing of the first and second solid-state imaging devices. A signal processing circuit performs a predetermined imaging process on the selected image signal to generate image data. The selection circuit alternately selects the first and second image signals at predetermined time intervals.

公开(公告)号：US20050062862A1

公开(公告)日：2005-03-24

申请号：US10941531

申请日：2004-09-15

申请人： Hisashi Matsuyama ,  Tohru Watanabe

发明人： Hisashi Matsuyama ,  Tohru Watanabe

IPC分类号： H01L27/148 ,  H01L27/14 ,  H01L29/765 ,  H04N5/335 ,  H04N5/341 ,  H04N5/367 ,  H04N5/369 ,  H04N5/372 ,  H04N5/378 ,  H04N9/64

CPC分类号： H04N5/3675 ,  H04N5/361

摘要： A signal processing apparatus including a clamp pulse generation circuit for generating a clamp pulse in synchronization with an image signal, a clamp circuit for clamping a signal of a black reference value in response to the clamp pulse, and a defect detection circuit for detecting a defective pixel included in an optical black area, wherein the clamp pulse generation circuit cancels a rise of the clamp pulse when a position of the defective pixel detected by the defect detecting circuit and a position of a rise state of the clamp pulse overlap with each other.

摘要翻译： 一种信号处理装置，包括用于产生与图像信号同步的钳位脉冲的钳位脉冲发生电路，用于钳位脉冲响应于黑参考值的信号的钳位电路，以及用于检测有缺陷的缺陷检测电路 包括在光学黑色区域中的像素，其中当由缺陷检测电路检测到的缺陷像素的位置和钳位脉冲的上升状态的位置彼此重叠时，钳位脉冲发生电路消除钳位脉冲的上升。