公开(公告)号：US08022305B2

公开(公告)日：2011-09-20

申请号：US12428860

申请日：2009-04-23

申请人： Takashi Yui ,  Atsushi Saiki

发明人： Takashi Yui ,  Atsushi Saiki

IPC分类号： H05K1/00

CPC分类号： H05K3/0052 ,  H05K3/005 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2203/167 ,  Y10T29/4913

摘要： A semiconductor device fabrication method includes: forming an elongated hole 5 in a wiring board plate along a perimeter line 3 of a plurality of wiring board regions defined over the wiring board plate with a connecting portion left unremoved at a corner of each of the wiring board regions; mounting semiconductor elements on the wiring board regions; and cutting the connecting portion using a punch 8 to isolate the wiring board regions from the wiring board plate into wiring boards. Each of the wiring boards has a cut edge formed by the punch, the cut edge starting from an end of the elongated hole 5 provided on a first side of the perimeter line 3 and extending across part of the connecting portion inside the perimeter line 3, the cut edge being angled inward of the wiring board so as to slope downward from the end of the elongated hole 5.

摘要翻译： 半导体器件制造方法包括：沿着布线板板上限定的多个布线板区域的周边线3在布线板板上形成细长孔5，其中连接部分在左边未被移除在每个布线板的拐角处 区域; 将半导体元件安装在布线板区域上; 并使用冲头8切割连接部分，以将布线板区域与布线板板隔离成线路板。 每个布线板具有由冲头形成的切割边缘，切割边缘从设置在周边线3的第一侧上的细长孔5的端部开始并延伸穿过周边线3内的连接部分的一部分， 切割边缘从布线板向内倾斜，从而从细长孔5的端部向下倾斜。

公开(公告)号：US08716868B2

公开(公告)日：2014-05-06

申请号：US12783836

申请日：2010-05-20

申请人： Takeshi Kawabata ,  Takashi Yui

发明人： Takeshi Kawabata ,  Takashi Yui

IPC分类号： H01L23/48

CPC分类号： H01L23/49838 ,  H01L23/49811 ,  H01L23/49827 ,  H01L25/105 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00 ,  H01L2924/00014

摘要： A pad (15) is provided on a surface connecting a first substrate (11) of a lower layer module with an upper layer module, the pad is partially covered by an insulating film (20) to form an opening section (3) exposing the pad (15), a first connection terminal (2) is formed on the lower surface of the first substrate (11) of the lower layer module, the planar shape of the opening section (3) is different from the planar shape of the first connection terminal (2), the outer shape of the opening section (3) is larger than the first connection terminal (2), and in a transmissive inspection from above, the shape of the lower end of a second connection terminal (30) spreading in the opening section (3) is not concealed by the other terminal. This configuration enables easy and reliable determination of whether bonding sections are satisfactory by a non-destructive inspection.

摘要翻译： 在连接下层模块的第一基板（11）与上层模块的表面上设置焊盘（15），所述焊盘部分被绝缘膜（20）覆盖以形成露出 衬垫（15），在下层模块的第一衬底（11）的下表面上形成第一连接端子（2），开口部分（3）的平面形状不同于第一衬底 连接端子（2），开口部（3）的外形大于第一连接端子（2），在从上方透射检查中，第二连接端子（30）的下端的形状扩展 在开口部（3）中没有被另一个端子隐藏。 该结构能够通过非破坏性检查来容易且可靠地确定接合部分是否令人满意。

公开(公告)号：US08330266B2

公开(公告)日：2012-12-11

申请号：US12721067

申请日：2010-03-10

申请人： Takashi Yui

发明人： Takashi Yui

IPC分类号： H01L23/52

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/13 ,  H01L23/16 ,  H01L24/32 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/15311 ,  H01L2924/00

摘要： A semiconductor device includes: a first semiconductor device including an interconnect substrate having a cavity structure and a semiconductor element mounted on a bottom part of the cavity structure; and a second semiconductor device provided on and connected to the first semiconductor device via connection terminals. A sealing material is provided between the first semiconductor device and the second semiconductor device. A sloped portion is formed, at a corner portion at which the bottom part and a side wall of the cavity structure in the first semiconductor device meets, to be sloped toward a center part of the cavity structure and have a tapered shape which becomes continuously wider in the direction from an upper part to a lower part.

摘要翻译： 半导体器件包括：第一半导体器件，包括具有腔结构的互连衬底和安装在腔结构的底部上的半导体元件; 以及经由连接端子设置并连接到第一半导体器件的第二半导体器件。 在第一半导体器件和第二半导体器件之间提供密封材料。 在第一半导体器件中的空腔结构的底部和侧壁相交的角部形成倾斜部，朝向空腔结构的中心部倾斜，并且具有逐渐变宽的锥形形状 在从上部到下部的方向上。

公开(公告)号：US20050003580A1

公开(公告)日：2005-01-06

申请号：US10881044

申请日：2004-06-30

申请人： Yoshiyuki Arai ,  Takashi Yui ,  Fumito Itou ,  Yasutake Yaguchi ,  Toshitaka Akahoshi

发明人： Yoshiyuki Arai ,  Takashi Yui ,  Fumito Itou ,  Yasutake Yaguchi ,  Toshitaka Akahoshi

IPC分类号： H01L25/18 ,  H01L21/60 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip. Thereby, influences of the fillet made of the adhesive are suppressed, allowing miniaturization of the device and improvement in the mass-productivity.

摘要翻译： 一种堆叠式芯片半导体器件，包括：具有电极焊盘的衬底; 第一半导体芯片，其经由第一粘合剂层倒装芯片封装在所述基板上; 第二半导体芯片，其安装在所述第一半导体芯片的上部并且具有电极焊盘; 用于电连接第二半导体芯片的电极焊盘和基板的电极焊盘的导线; 以及用于封装第一半导体芯片，第二半导体芯片和电线的模制树脂，第一粘合剂层在第一半导体芯片的周围形成圆角。 第一半导体芯片以其中心轴偏离基板的中心轴线的方式设置，偏移被设置成使得第一半导体芯片朝向与圆角的边缘的最大长度相反的一侧偏移 第一个半导体芯片。 由此，抑制了由粘合剂制成的圆角的影响，从而使装置小型化并提高了批量生产率。

公开(公告)号：US07298043B2

公开(公告)日：2007-11-20

申请号：US11375134

申请日：2006-03-15

申请人： Takashi Yui

发明人： Takashi Yui

IPC分类号： H01L23/367

CPC分类号： H01L23/3677 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor device having a wiring substrate, a semiconductor element mounted on the wiring substrate via a heat sink, a wire electrically connecting the wiring substrate and the semiconductor element, the wiring substrate having through holes each connected to the wire or the heat sink, and external electrodes formed on a back surface of the wiring substrate and connected to the through holes. An insulating layer is formed between the heat sink and the semiconductor element, and the heat sink is divided into at least two sections. Hence, the back surface of the semiconductor element maintains an electrically disconnected state irrespective of the potential of the heat sink, and the heat dissipation design is allowed greater flexibility. Thus, the external electrodes connected to the heat sink via the through holes are connected to the mounting substrate wirings having satisfactory heat dissipation efficiency, allowing the heat of the semiconductor element to escape efficiently.

摘要翻译： 一种具有布线基板的半导体器件，经由散热器安装在布线基板上的半导体元件，将布线基板与半导体元件电连接的布线，具有各自与导线或散热片连接的通孔的布线基板，以及 外部电极形成在布线基板的背面并与通孔连接。 在散热片和半导体元件之间形成绝缘层，将散热片分成至少两个部分。 因此，与散热器的电位无关地，半导体元件的背面保持电断开状态，并且允许散热设计更大的灵活性。 因此，通过通孔连接到散热器的外部电极与具有令人满意的散热效率的安装基板布线连接，从而使半导体元件的热量有效地逸出。

公开(公告)号：US07082923B2

公开(公告)日：2006-08-01

申请号：US11049648

申请日：2005-02-04

申请人： Takashi Yui ,  Noboru Takagi ,  Kiyoo Hirose ,  Keizo Hiraku ,  Hirohiko Yamada

发明人： Takashi Yui ,  Noboru Takagi ,  Kiyoo Hirose ,  Keizo Hiraku ,  Hirohiko Yamada

IPC分类号： F02D3/00 ,  F02D41/00

CPC分类号： F02D41/083 ,  F01L1/185 ,  F01L13/0063 ,  F01L2001/0537 ,  F01L2105/00 ,  F01L2800/00 ,  F02D13/02 ,  F02D41/0002 ,  F02D41/086 ,  F02D41/1454 ,  F02D2200/023 ,  F02D2200/0404 ,  Y02T10/18 ,  Y02T10/42

摘要： An controller detects a change in a load generation state of an accessory device that generates a load on the internal combustion engine during operation, and the controller in turn controls a variable valve mechanism to change at least one of an operation angle and a valve lift of an intake valve of the internal combustion engine, as well as changing an amount of an intake air drawn into the internal combustion engine, in response to the detected change in the load generation state of the accessory device.

摘要翻译： 控制器检测在操作期间在内燃机上产生负载的附件装置的负载生成状态的变化，并且控制器进而控制可变气门机构以改变操作角和气门升程中的至少一个 内燃机的进气阀，以及响应于检测到的附件装置的负载产生状态的变化而改变吸入内燃机的进气量。

公开(公告)号：US06693347B2

公开(公告)日：2004-02-17

申请号：US10320405

申请日：2002-12-17

申请人： Hiroaki Fujimoto ,  Yoshinobu Kunitomo ,  Takashi Yui

发明人： Hiroaki Fujimoto ,  Yoshinobu Kunitomo ,  Takashi Yui

IPC分类号： H01L2302

CPC分类号： H01L25/0657 ,  H01L25/0652 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/0401

摘要： A semiconductor device includes: a wiring board; a first semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which is electrically connected to the wiring board via a raised electrode, the circuitry side of the first chip facing the principal surface of the wiring board; and a second semiconductor chip, which has a circuitry side and a non-circuitry side that face each other vertically and which includes an external electrode on the circuitry side thereof. The non-circuitry sides of the first and second semiconductor chips are secured to each other. The external electrode of the second semiconductor chip is connected to the wiring board via a metal fine wire. The external and raised electrodes are so disposed as not to overlap each other as viewed vertically downward from over the principal surface of the wiring board.

摘要翻译： 一种半导体器件，包括：布线板; 第一半导体芯片，其具有垂直相对的电路侧和非电路侧，并且经由凸起电极电连接到布线板，第一芯片的电路侧面对布线板的主表面 ; 以及第二半导体芯片，其具有垂直彼此面对并且在其电路侧上包括外部电极的电路侧和非电路侧。 第一和第二半导体芯片的非电路侧彼此固定。 第二半导体芯片的外部电极通过金属细线连接到布线板。 外电极和凸起电极被布置为从布线板的主表面的垂直向下观察不彼此重叠。

公开(公告)号：US07964475B2

公开(公告)日：2011-06-21

申请号：US11951441

申请日：2007-12-06

申请人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

发明人： Yukiko Haraguchi ,  Takahiro Kumakawa ,  Takashi Yui ,  Kazumi Watase

IPC分类号： H01L27/00 ,  H01L21/82

CPC分类号： H01L21/78

摘要： A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.

摘要翻译： 在切割区域3的切割点的外侧形成改质层5和改质层8.因此，在切割点的不同物理性质之间不形成另一界面，可以防止从界面 在半导体元件2和半导体基板1之间以及在切割期间从半导体元件的表面，从而抑制了对半导体元件的切屑的发展。

公开(公告)号：US07521288B2

公开(公告)日：2009-04-21

申请号：US11717953

申请日：2007-03-14

申请人： Yoshiyuki Arai ,  Takashi Yui ,  Fumito Itou ,  Yasutake Yaguchi ,  Toshitaka Akahoshi

发明人： Yoshiyuki Arai ,  Takashi Yui ,  Fumito Itou ,  Yasutake Yaguchi ,  Toshitaka Akahoshi

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip. Thereby, influences of the fillet made of the adhesive are suppressed, allowing miniaturization of the device and improvement in the mass-productivity.

摘要翻译： 一种堆叠式芯片半导体器件，包括：具有电极焊盘的衬底; 第一半导体芯片，其经由第一粘合剂层倒装芯片封装在所述基板上; 第二半导体芯片，其安装在所述第一半导体芯片的上部并且具有电极焊盘; 用于电连接第二半导体芯片的电极焊盘和基板的电极焊盘的导线; 以及用于封装第一半导体芯片，第二半导体芯片和电线的模制树脂，第一粘合剂层在第一半导体芯片的周围形成圆角。 第一半导体芯片以其中心轴偏离基板的中心轴线的方式设置，偏移被设置成使得第一半导体芯片朝向与圆角的边缘的最大长度相反的一侧偏移 第一个半导体芯片。 由此，抑制了由粘合剂制成的圆角的影响，从而使装置小型化并提高了批量生产率。

公开(公告)号：US07239021B2

公开(公告)日：2007-07-03

申请号：US10881044

申请日：2004-06-30

申请人： Yoshiyuki Arai ,  Takashi Yui ,  Fumito Itou ,  Yasutake Yaguchi ,  Toshitaka Akahoshi

发明人： Yoshiyuki Arai ,  Takashi Yui ,  Fumito Itou ,  Yasutake Yaguchi ,  Toshitaka Akahoshi

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L23/3121 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip. Thereby, influences of the fillet made of the adhesive are suppressed, allowing miniaturization of the device and improvement in the mass-productivity.