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    Memory including transistors with double floating gate structures
    1.
    发明授权
    Memory including transistors with double floating gate structures 失效
    存储器包括具有双浮栅结构的晶体管

    公开(公告)号：US08610196B2

    公开(公告)日：2013-12-17

    申请号：US13608436

    申请日：2012-09-10

    申请人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    发明人： Tetsufumi Tanamoto ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    IPC分类号： H01L27/11

    CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

    摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

    摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

    MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES
    2.
    发明申请
    MEMORY INCLUDING TRANSISTORS WITH DOUBLE FLOATING GATE STRUCTURES 失效
    包含两个浮动门结构的晶体管的存储器

    公开(公告)号：US20130069134A1

    公开(公告)日：2013-03-21

    申请号：US13608436

    申请日：2012-09-10

    申请人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    发明人： Tetsufumi TANAMOTO ,  Kosuke Tatsumura ,  Kiwamu Sakuma ,  Atsuhiro Kinoshita ,  Shinobu Fujita ,  Koichi Muraoka

    IPC分类号： H01L27/11

    CPC分类号： H01L29/42332 ,  G11C11/412 ,  G11C14/0063 ,  H01L27/1104 ,  H01L29/7881

    摘要： In a memory of an embodiment, first and second P-channel transistors are formed on a first semiconductor region, and each of the first and second P-channel transistors has a structure formed by stacking a first insulating film, a first floating gate, a second insulating film, a second floating gate, a third insulating film, and a first control gate in this order on the first semiconductor region. In the memory, first and second N-channel transistors are formed on a second semiconductor region, and each of the first and second N-channel transistors has a structure formed by stacking a fourth insulating film, a third floating gate, a fifth insulating film, a fourth floating gate, a sixth insulating film, and a second control gate in this order on the second semiconductor region.

    摘要翻译： 在实施例的存储器中，第一和第二P沟道晶体管形成在第一半导体区域上，并且第一和第二P沟道晶体管中的每一个具有通过堆叠第一绝缘膜，第一浮动栅极， 第二绝缘膜，第二浮栅，第三绝缘膜和第一控制栅极。 在存储器中，第一和第二N沟道晶体管形成在第二半导体区域上，并且第一和第二N沟道晶体管中的每一个具有通过堆叠第四绝缘膜，第三浮栅，第五绝缘膜 ，第四浮栅，第六绝缘膜和第二控制栅极。

    Nonvolatile programmable logic switch
    3.
    发明授权
    Nonvolatile programmable logic switch 有权
    非易失性可编程逻辑开关

    公开(公告)号：US08553464B2

    公开(公告)日：2013-10-08

    申请号：US13240087

    申请日：2011-09-22

    申请人： Yoshifumi Nishi ,  Daisuke Hagishima ,  Shinichi Yasuda ,  Tetsufumi Tanamoto ,  Takahiro Kurita ,  Atsuhiro Kinoshita ,  Shinobu Fujita

    发明人： Yoshifumi Nishi ,  Daisuke Hagishima ,  Shinichi Yasuda ,  Tetsufumi Tanamoto ,  Takahiro Kurita ,  Atsuhiro Kinoshita ,  Shinobu Fujita

    IPC分类号： G11C11/35

    CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/10 ,  H01L27/11573 ,  H01L27/11803

    摘要： An aspect of the present embodiment, there is provided a nonvolatile programmable logic switch including a first memory cell transistor, a second memory cell transistor, a pass transistor and a first substrate electrode applying a substrate voltage to the pass transistor, wherein a writing voltage is applied to the first wiring, a first voltage is applied to one of a second wiring and a third wiring and a second voltage which is lower than the first voltage is applied to the other of the second wiring and the third wiring, and the first substrate voltage which is higher than the second voltage and lower than the first voltage is applied to a well of the pass transistor, when data is written into the first memory cell transistor or the second memory cell transistor.

    摘要翻译： 本实施例的一个方面提供了一种非易失性可编程逻辑开关，包括第一存储单元晶体管，第二存储单元晶体管，传输晶体管和向该通过晶体管施加衬底电压的第一衬底电极，其中写入电压为 施加到第一布线，第一电压施加到第二布线和第三布线中的一个，并且低于第一电压的第二电压施加到第二布线和第三布线中的另一布线，第一基板 当数据被写入第一存储单元晶体管或第二存储单元晶体管时，高于第二电压并低于第一电压的电压被施加到传输晶体管的阱。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 审中-公开
    半导体集成电路

    公开(公告)号：US20130307054A1

    公开(公告)日：2013-11-21

    申请号：US13606292

    申请日：2012-09-07

    申请人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

    发明人： Shinichi YASUDA ,  Kosuke Tatsumura ,  Mari Matsumoto ,  Koichiro Zaitsu ,  Masato Oda ,  Atsuhiro Kinoshita ,  Daisuke Hagishima ,  Yoshifumi Nishi ,  Takahiro Kurita ,  Shinobu Fujita

    IPC分类号： H01L27/105

    CPC分类号： G11C16/10 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/11526 ,  H01L27/11573 ,  H01L29/7881 ,  H01L29/792

    摘要： One embodiment provides a semiconductor integrated circuit, including: a substrate; a plurality of nonvolatile memory portions formed in the substrate, each including a first nonvolatile memory and a second nonvolatile memory; and a plurality of logic transistor portions formed in the substrate, each including at least one of logic transistor, wherein the logic transistors include: a first transistor which is directly connected to drains of the first and second nonvolatile memories at its gate; and a second transistor which is not directly connected to the drains of the first and second nonvolatile memories, and wherein a bottom surface of the gate of each of the logic transistors sandwiching the first and second nonvolatile memories is lower in height from a top surface of the substrate than a bottom surface of the control gate of each of the first and second nonvolatile memories.

    摘要翻译： 一个实施例提供一种半导体集成电路，包括：基板; 形成在所述基板中的多个非易失性存储部，每个包括第一非易失性存储器和第二非易失性存储器; 以及形成在所述衬底中的多个逻辑晶体管部分，每个逻辑晶体管部分包括逻辑晶体管中的至少一个，其中所述逻辑晶体管包括：第一晶体管，其第一和第二非易失性存储器的栅极直接连接到第一晶体管; 以及第二晶体管，其不直接连接到第一和第二非易失性存储器的漏极，并且其中夹着第一和第二非易失性存储器的每个逻辑晶体管的栅极的底表面的高度与 所述基板比所述第一和第二非易失性存储器中的每一个的所述控制栅极的底表面。

    RANDOM NUMBER GENERATION DEVICE
    6.
    发明申请
    RANDOM NUMBER GENERATION DEVICE 审中-公开
    随机数生成装置

    公开(公告)号：US20090309646A1

    公开(公告)日：2009-12-17

    申请号：US12391640

    申请日：2009-02-24

    申请人： Shigeki KOBAYASHI ,  Ken Uchida ,  Shinobu Fujita ,  Tetsufumi Tanamoto

    发明人： Shigeki KOBAYASHI ,  Ken Uchida ,  Shinobu Fujita ,  Tetsufumi Tanamoto

    IPC分类号： G06G7/12 ,  H01L27/088

    CPC分类号： H01L29/1054 ,  G06F7/588 ,  H01L21/823807 ,  H01L27/088 ,  H01L29/7843 ,  H03K3/84

    摘要： A random number generation device includes: a first source region; a first drain region; a first channel region provided between the first source region and the first drain region; a first insulating film provided on the first channel region; and a first gate electrode provided on the first insulating film. The first insulating film has a trap capturing and releasing a charge, and a tensile or compressive stress is applied in a direction of a gate length to at least one of the first channel region and the first insulating film.

    摘要翻译： 随机数生成装置包括：第一源区域; 第一漏区; 设置在所述第一源极区域和所述第一漏极区域之间的第一沟道区域; 设置在所述第一沟道区上的第一绝缘膜; 以及设置在第一绝缘膜上的第一栅电极。 第一绝缘膜具有陷阱捕获和释放电荷，并且在栅极长度方向上向第一沟道区和第一绝缘膜中的至少一个施加拉伸或压缩应力。

    RANDOM NUMBER GENERATING DEVICE
    8.
    发明申请
    RANDOM NUMBER GENERATING DEVICE 失效
    随机数生成装置

    公开(公告)号：US20080251783A1

    公开(公告)日：2008-10-16

    申请号：US12143124

    申请日：2008-06-20

    申请人： Tetsufumi TANAMOTO ,  Shinobu Fujita

    发明人： Tetsufumi TANAMOTO ,  Shinobu Fujita

    IPC分类号： H01L29/00

    CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

    摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

    摘要翻译： 目的是提供具有较小的电路尺寸和较小的输出偏压值的随机数产生装置。 随机数产生装置包括彼此平行布置的一对第一和第二电流路径，以及一对可互相交换电荷并位于第一和第二电流路径附近的第一和第二细颗粒 。

    Random number generating device
    9.
    发明授权
    Random number generating device 有权
    随机数生成装置

    公开(公告)号：US08330160B2

    公开(公告)日：2012-12-11

    申请号：US12143206

    申请日：2008-06-20

    申请人： Tetsufumi Tanamoto ,  Shinobu Fujita

    发明人： Tetsufumi Tanamoto ,  Shinobu Fujita

    IPC分类号： H01L23/58

    CPC分类号： B82Y10/00 ,  G06F7/588 ,  H01L29/7888 ,  H04L9/0861

    摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

    摘要翻译： 目的是提供具有较小电路尺寸和较小输出偏置值的随机数产生装置。 随机数产生装置包括彼此平行布置的一对第一和第二电流路径，以及一对可互相交换电荷并位于第一和第二电流路径附近的第一和第二细颗粒 。

    Random number test circuit
    10.
    发明申请
    Random number test circuit 有权
    随机数测试电路

    公开(公告)号：US20070162806A1

    公开(公告)日：2007-07-12

    申请号：US11635590

    申请日：2006-12-08

    申请人： Mari Matsumoto ,  Tetsufumi Tanamoto ,  Shinobu Fujita

    发明人： Mari Matsumoto ,  Tetsufumi Tanamoto ,  Shinobu Fujita

    IPC分类号： G01R31/28

    CPC分类号： G06F7/58 ,  G06F17/15

    摘要： The random number test circuit includes a shift register which operates based on a clock and which successively stores serial random numbers generated by a random number generation element, a first random number being output from a predetermined stage of the shift register; a comparison circuit which compares the first random number with a second random number located at a distance of a first predetermined number of bits from the first random number, the second random number being generated by the random number generation element; a counter which counts a frequency of occurrence of equality or inequality between the first random number and the second random number, with respect to all bits in the serial random numbers, and a decision circuit which judges an article quality to be good if a count value in the counter indicates a frequency of occurrence equal to or less than a number determined previously by correlation.

    摘要翻译： 该随机数测试电路包括一个移位寄存器，该移位寄存器基于时钟进行操作，并连续地存储由随机数生成元件生成的串行随机数，第一随机数从移位寄存器的预定级输出; 比较电路，其将所述第一随机数与位于距所述第一随机数的第一预定位数的距离的第二随机数进行比较，所述第二随机数由所述随机数生成元生成; 相对于串行随机数中的所有比特来计算第一随机数和第二随机数之间的相等或不等式的发生频率的计数器，以及判断电路，如果计数值 在计数器中表示发生的频率等于或小于先前通过相关性确定的数字。