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    Delay-locked loop
    1.
    发明授权
    Delay-locked loop 失效
    延迟锁定环路

    公开(公告)号：US5614855A

    公开(公告)日：1997-03-25

    申请号：US512597

    申请日：1995-08-21

    申请人： Thomas H. Lee ,  Kevin S. Donnelly ,  Tsyr-Chyang Ho ,  Mark G. Johnson

    发明人： Thomas H. Lee ,  Kevin S. Donnelly ,  Tsyr-Chyang Ho ,  Mark G. Johnson

    IPC分类号： G01R31/28 ,  H03L7/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/093 ,  H03K5/13

    CPC分类号： H03L7/0812

    摘要： A delay locked loop (DLL) is described in which a phase detector compares the phase of the output of the DLL with that of a reference input. The output of the phase comparator drives a differential charge pump which functions to integrate the phase comparator output signal over time. The charge pump output controls a phase shifter with unlimited range that adjusts the phase of the DLL output so that the output of the phase comparator is high 50% of the time on average. Because the DLL adjusts the phase shifter until the output of the phase detector is high 50% of the time, on average, the relationship of the DLL output clock to the input reference clock depends only on the type of phase detector used. For example, when a data receiver is used as the phase detector in the DLL, the output of the DLL is a clock signal which can be used as a sampling clock for data receivers elsewhere in the system, and is timed to sample data at the optional instant independent of temperature, supply voltage and process variations. Alternatively, a quadrature phase detector may be employed to generate a clock signal that possesses a quadrature (90.degree. ) relationship with a reference clock signal input. This may be used, for example, to generate a transmit clock for a data transmission device. Furthermore, the DLL is controlled to minimize dither jitter while minimizing acquisition time. In addition, duty cycle correcting amplifiers are employed to produce a DLL output clock that has a desired duty cycle, for example 50%. Additionally, the inputs to the charge pump are reversed in alternate quadrants of the phase plane in order to enable unlimited phase shift with a finite control voltage range.

    摘要翻译： 描述了延迟锁定环（DLL），其中相位检测器将DLL的输出的相位与参考输入的相位进行比较。 相位比较器的输出驱动一个差分电荷泵，用于对相位比较器输出信号随时间进行积分。 电荷泵输出控制无限幅度的移相器，可调节DLL输出的相位，使相位比较器的输出平均高达50％的时间。 因为DLL调整移相器，直到相位检测器的输出高达50％的时间，平均而言，DLL输出时钟与输入参考时钟的关系仅取决于所使用的相位检测器的类型。 例如，当数据接收器用作DLL中的相位检测器时，DLL的输出是可以用作系统中其他地方的数据接收器的采样时钟的时钟信号，并且被定时以在 可选速度独立于温度，电源电压和工艺变化。 或者，可以采用正交相位检测器来产生与参考时钟信号输入具有正交（90°）关系的时钟信号。 这可以用于例如为数据传输设备产生传输时钟。 此外，DLL被控制以最小化抖动抖动，同时最小化采集时间。 此外，采用占空比校正放大器来产生具有期望占空比的DLL输出时钟，例如50％。 此外，电荷泵的输入在相平面的交替象限中反转，以便在有限的控制电压范围内实现无限相移。

    Delay locked loop circuitry for clock delay adjustment
    3.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 有权
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US06539072B1

    公开(公告)日：2003-03-25

    申请号：US09524402

    申请日：2000-03-13

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H04L700

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Delay-locked loop circuitry for clock delay adjustment
    4.
    发明授权
    Delay-locked loop circuitry for clock delay adjustment 失效
    用于时钟延迟调整的延迟锁定环路

    公开(公告)号：US6125157A

    公开(公告)日：2000-09-26

    申请号：US795657

    申请日：1997-02-06

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark

    IPC分类号： G06F1/10 ,  G11C7/22 ,  H03K5/00 ,  H03K5/13 ,  H03K5/24 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0037 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H04L7/0008 ,  H04L7/0025

    摘要： Delay-locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a set of delay-producing elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used.

    摘要翻译： 延迟锁定环路电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的一组延迟产生元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据使用的单位延迟数，输入和输出时钟之间的不同相位关系是可能的。

    Delay locked loop circuitry for clock delay adjustment
    5.
    发明授权
    Delay locked loop circuitry for clock delay adjustment 失效
    延迟锁定环电路，用于时钟延迟调整

    公开(公告)号：US07039147B2

    公开(公告)日：2006-05-02

    申请号：US10366865

    申请日：2003-02-14

    申请人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    发明人： Kevin S. Donnelly ,  Pak Shing Chau ,  Mark A. Horowitz ,  Thomas H. Lee ,  Mark G. Johnson ,  Benedict C. Lau ,  Leung Yu ,  Bruno W. Garlepp ,  Yiu-Fai Chan ,  Jun Kim ,  Chanh Vi Tran ,  Donald C. Stark ,  Nhat M. Nguyen

    IPC分类号： H03D3/24

    CPC分类号： H03K5/133 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/2481 ,  H03K2005/00026 ,  H03K2005/00032 ,  H03K2005/00052 ,  H03K2005/00208 ,  H03L7/07 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0814 ,  H04L7/0008 ,  H04L7/0025 ,  H04L7/0037

    摘要： Delay locked loop circuitry for generating a predetermined phase relationship between a pair of clocks. A first delay-locked loop includes a delay elements arranged in a chain, the chain receiving an input clock and generating, from each delay element, a set of phase vectors, each shifted a unit delay from the adjacent vector. The first delay-locked loop adjusts the unit delays in the delay chain using a delay adjustment signal so that the phase vectors span a predetermined phase shift of the input clock. A second delay-locked loop selects, from the first delay-locked loop, a pair of phase vectors which brackets the phase of an input clock. A phase interpolator receives the selected pair of vectors and generates an output clock and a delayed output clock, the amount of the delay being controlled by the delay adjustment signal of the first delay-locked loop circuitry. A phase detector compares the delayed output clock with the input clock and adjusts the phase interpolator, based on the phase comparison, so that the phase of the delayed output clock is in phase with the input clock. As a result, there is a predetermined phase relationship between the output clock and the input clock, the phase relationship being the amount of delay between the output clock and the delayed output clock. Different phase relationships between the input and output clock are possible depending on the number of unit delays used in the path of the, delayed output clock or the output clock.

    摘要翻译： 延迟锁定环电路，用于在一对时钟之间产生预定的相位关系。 第一延迟锁定环包括布置在链中的延迟元件，所述链接收输入时钟，并且从每个延迟元件产生一组相位矢量，每组相移向量从相邻矢量移位单位延迟。 第一延迟锁定环路使用延迟调整信号来调整延迟链中的单元延迟，使得相位矢量跨越输入时钟的预定相移。 第二延迟锁定环路从第一延迟锁定环路中选择一对相对于输入时钟相位的相位矢量。 相位插值器接收所选择的一对矢量，并产生输出时钟和延迟输出时钟，延迟量由第一延迟锁定环电路的延迟调整信号控制。 相位检测器将延迟的输出时钟与输入时钟进行比较，并根据相位比较调节相位内插器，使得延迟输出时钟的相位与输入时钟同相。 结果，在输出时钟和输入时钟之间存在预定的相位关系，相位关系是输出时钟和延迟的输出时钟之间的延迟量。 根据在延迟输出时钟或输出时钟的路径中使用的单位延迟的数量，输入和输出时钟之间的不同相位关系是可能的。

    Zero power reset circuit for low voltage CMOS circuits
    6.
    发明授权
    Zero power reset circuit for low voltage CMOS circuits 失效
    用于低压CMOS电路的零功率复位电路

    公开(公告)号：US6107847A

    公开(公告)日：2000-08-22

    申请号：US000717

    申请日：1997-12-30

    申请人： Mark G. Johnson ,  Kevin S. Donnelly ,  Clemenz L. Portmann

    发明人： Mark G. Johnson ,  Kevin S. Donnelly ,  Clemenz L. Portmann

    IPC分类号： H03K3/356 ,  H03K17/22 ,  H03L7/00

    CPC分类号： H03K17/223 ,  H03K3/356008

    摘要： A pulse generating circuit that includes an unbalanced latch and a feedback circuit. The unbalanced latch is configured to generate a latch signal having a predetermined state in response to application of power to the circuit. The feedback circuit is coupled in a negative feedback arrangement with the unbalanced latch and generates a pulse signal for a predetermined period of time in response to the latch signal.

    摘要翻译： 一种包括不平衡锁存器和反馈电路的脉冲发生电路。 不平衡锁存器被配置为响应于向电路施加电力而产生具有预定状态的锁存信号。 反馈电路以负反馈装置与不平衡锁存器耦合，并响应于锁存信号产生预定时间段的脉冲信号。