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    Composition and method for micro etching of copper and copper alloys
    2.
    发明授权
    Composition and method for micro etching of copper and copper alloys 有权
    铜和铜合金微蚀刻的组成和方法

    公开(公告)号：US08758634B2

    公开(公告)日：2014-06-24

    申请号：US13634913

    申请日：2010-05-26

    申请人： Dirk Tews ,  Christian Sparing ,  Martin Thoms

    发明人： Dirk Tews ,  Christian Sparing ,  Martin Thoms

    IPC分类号： H01B13/00

    CPC分类号： C23F1/18 ,  H05K3/28 ,  H05K3/383

    摘要： Disclosed is a composition for and applying said method for micro etching of copper or copper alloys during manufacture of printed circuit boards. Said composition comprises a copper salt, a source of halide ions, a buffer system and a benzothiazole compound as an etch refiner. The inventive composition and method is especially useful for manufacture of printed circuit boards having structural features of ≦100 μm.

    摘要翻译： 公开了一种用于印刷电路板制造过程中用于和应用所述铜或铜合金微蚀刻方法的组合物。 所述组合物包含铜盐，卤离子源，缓冲体系和苯并噻唑化合物作为蚀刻精炼机。 本发明的组合物和方法对于具有结构特征为＆amp;100μm的印刷电路板的制造特别有用。

    COMPOSITION AND METHOD FOR MICRO ETCHING OF COPPER AND COPPER ALLOYS
    3.
    发明申请
    COMPOSITION AND METHOD FOR MICRO ETCHING OF COPPER AND COPPER ALLOYS 有权
    铜和铜合金的微蚀刻的组合物和方法

    公开(公告)号：US20130056438A1

    公开(公告)日：2013-03-07

    申请号：US13634913

    申请日：2010-05-26

    申请人： Dirk Tews ,  Christian Sparing ,  Martin Thoms

    发明人： Dirk Tews ,  Christian Sparing ,  Martin Thoms

    IPC分类号： C23F1/18 ,  H05K3/22 ,  C09K13/08 ,  C09K13/00 ,  C09K13/06

    CPC分类号： C23F1/18 ,  H05K3/28 ,  H05K3/383

    摘要： Disclosed is a composition for and applying said method for micro etching of copper or copper alloys during manufacture of printed circuit boards. Said composition comprises a copper salt, a source of halide ions, a buffer system and a benzothiazole compound as an etch refiner. The inventive composition and method is especially useful for manufacture of printed circuit boards having structural features of ≦100 μm.

    摘要翻译： 公开了一种用于印刷电路板制造过程中用于和应用所述铜或铜合金微蚀刻方法的组合物。 所述组合物包含铜盐，卤离子源，缓冲体系和苯并噻唑化合物作为蚀刻精炼机。 本发明的组合物和方法对于具有结构特征为＆amp;100μm的印刷电路板的制造特别有用。

    Method of Manufacturing a Circuit Carrier Layer and a Use of Said Method for Manufacturing a Circuit Carrier
    6.
    发明申请
    Method of Manufacturing a Circuit Carrier Layer and a Use of Said Method for Manufacturing a Circuit Carrier 审中-公开
    制造电路载体层的方法和所述制造电路载体的方法的用途

    公开(公告)号：US20120118753A1

    公开(公告)日：2012-05-17

    申请号：US13260756

    申请日：2010-03-30

    申请人： Norbert Lützow ,  Christian Sparing ,  Dirk Tews ,  Martin Thoms

    发明人： Norbert Lützow ,  Christian Sparing ,  Dirk Tews ,  Martin Thoms

    IPC分类号： H05K3/46 ,  C25D5/02

    CPC分类号： H05K3/205 ,  H05K2203/124

    摘要： In order to be able to produce high density circuits on a dielectric substrate wherein the conductor lines of said circuit have a good adhesion to the dielectric substrate surface, a method is provided which comprises the following method steps: a) providing an auxiliary substrate having two sides, at least one of said sides having an electrically conductive surface; b) treating at least one of the at least one electrically conductive surface with at least one release layer forming compound, the at least one release layer forming compound being a heterocyclic compound having at least one thiol group, c) forming a patterned resist coating on at least one of said at least one electrically conductive surface which has been treated with said at least one release layer forming compound, the patterned resist coating having at least one resist opening thereby exposing the electrically conductive surface; d) forming an electrically conductive pattern in the at least one resist opening by electrodepositing a metal on the exposed electrically conductive surface; e) embedding each electrically conductive pattern into a dielectric material by forming a respective dielectric material layer on the respective side of the auxiliary substrate; and f) separating each dielectric material layer comprising the respective embedded electrically conductive pattern and the auxiliary substrate from each other.

    摘要翻译： 为了能够在电介质基板上制造高密度电路，其中所述电路的导体线对电介质基板表面具有良好的粘附性，提供了一种方法，其包括以下方法步骤：a）提供具有两个 所述侧面中的至少一个具有导电表面; b）用至少一种释放层形成化合物处理所述至少一个导电表面中的至少一个，所述至少一种形成隔离层的化合物是具有至少一个硫醇基的杂环化合物，c）在 所述至少一个导电表面中的至少一个已经用所述至少一个释放层形成化合物处理，所述图案化抗蚀剂涂层具有至少一个抗蚀剂开口，从而暴露所述导电表面; d）通过在暴露的导电表面上电沉积金属，在所述至少一个抗蚀剂开口中形成导电图案; e）通过在辅助基板的相应侧上形成相应的介电材料层，将每个导电图案嵌入电介质材料中; 以及f）将包括相应的嵌入的导电图案和辅助基板的每个介电材料层彼此分离。

    Process for etching a recessed structure filled with tin or a tin alloy
    7.
    发明授权
    Process for etching a recessed structure filled with tin or a tin alloy 有权
    用于蚀刻填充有锡或锡合金的凹陷结构的工艺

    公开(公告)号：US09332652B2

    公开(公告)日：2016-05-03

    申请号：US13979914

    申请日：2012-02-09

    申请人： Neal Wood ,  Dirk Tews

    发明人： Neal Wood ,  Dirk Tews

    IPC分类号： C23G1/02 ,  H05K3/26 ,  C23F1/40 ,  H01L21/321 ,  H01L21/3213 ,  H05K3/34 ,  H01L21/768

    CPC分类号： H05K3/26 ,  C23F1/40 ,  H01L21/32115 ,  H01L21/32134 ,  H01L21/7684 ,  H05K3/3473 ,  H05K2203/054 ,  H05K2203/0793

    摘要： A process for etching excess tin or tin alloy deposits including the steps of providing a substrate having recessed structures filled with tin or a tin alloy and an excess layer of tin or tin alloy, providing an aqueous etching solution consisting of a source of hydroxide ions and a nitro-substituted aromatic sulfonic acid and having a pH value greater than 7, and contacting said substrate with said aqueous etching solution for removing said excess tin or tin alloy layer on top of the recessed structures filled with tin or a tin alloy.

    摘要翻译： 一种用于蚀刻多余的锡或锡合金沉积物的方法，包括以下步骤：提供填充有锡或锡合金和过量的锡或锡合金层的凹陷结构的基底，提供由氢氧根离子源组成的水性蚀刻溶液， 硝基取代的芳族磺酸并且具有大于7的pH值，并使所述底物与所述水性蚀刻溶液接触，以便在填充有锡或锡合金的凹陷结构的顶部上除去所述多余的锡或锡合金层。