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公开(公告)号：US07132361B2
公开(公告)日：2006-11-07
申请号：US11020907
申请日：2004-12-23
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/67173 , H01L21/67207 , H05K1/0393 , H05K3/143 , H05K3/4076 , H05K3/467 , H05K2203/1545 , Y10S438/944 , Y10S438/945
摘要： Via holes are formed in a continuous inline shadow mask production system by depositing a first conductor layer and subsequently depositing a first insulator layer over a portion of the first conductor layer. The first insulator layer is deposited in a manner to define at least one notch along its edge. The second insulator layer is then deposited on another portion of the first conductor layer in a manner whereupon the second insulator layer slightly overlaps each notch of the first insulator layer, thereby forming the one or more via holes. A conductive filler can optionally be deposited in each via hole. Lastly, a second conductive layer can be deposited over the first insulator layer, the second insulator layer and, if provided, the conductive filler.
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公开(公告)号：US08348503B2
公开(公告)日：2013-01-08
申请号：US11764703
申请日：2007-06-18
IPC分类号： G01K3/00
CPC分类号： C23C14/562 , C23C14/042 , C23C14/541 , H01L51/0008 , H01L51/0023 , H01L51/529 , H01L51/56 , H01L2924/0002 , H01L2924/00
摘要： A system and method for providing an active array of temperature sensing and cooling elements, including an active heatsink which further includes an active temperature sensing layer, a thermoelectric cooling layer, and a heatsink, which further includes a plurality of cooling channels. The temperature sensing element within the active temperature sensing layer includes a plurality of switching transistors, a linear transistor, a current sense resistor, a thermistor, a voltage sensing bus, a voltage setting bus, a current measurement bus, a measurement switching bus, a sense control bus, a storage capacitor, and a supply voltage, all under the control of a process control computer. The method of using an active array of temperature sensing and cooling elements includes the steps of aligning the shadow mask, depositing the material, detecting a thermal gradient, and controlling the thermoelectric cooling.
摘要翻译： 一种用于提供温度感测和冷却元件的有源阵列的系统和方法，包括有源散热器，其还包括有源温度感测层，热电冷却层和散热器，其还包括多个冷却通道。 有源温度检测层内的温度检测元件包括多个开关晶体管，线性晶体管，电流检测电阻，热敏电阻，电压感测总线，电压设定总线，电流测量总线，测量开关总线， 感测控制总线，存储电容器和电源电压，全部由过程控制计算机控制。 使用温度感测和冷却元件的有源阵列的方法包括对准荫罩，沉积材料，检测热梯度和控制热电冷却的步骤。
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公开(公告)号：US07232694B2
公开(公告)日：2007-06-19
申请号：US10950646
申请日：2004-09-28
CPC分类号： C23C14/562 , C23C14/042 , C23C14/541 , H01L51/0008 , H01L51/0023 , H01L51/529 , H01L51/56 , H01L2924/0002 , H01L2924/00
摘要： A system and method for active array temperature sensing and cooling. The system includes an active temperature sensing layer, a thermoelectric cooling layer and a heatsink layer. The temperature sensing layer is formed of temperature sensing elements that sense the temperature gradient across an unevenly heated region of the active array substrate. The thermoelectric cooling layer controls the temperature gradient sensed by the temperature sensing layer. The heatsink layer includes a plurality of cooling channels for absorbing thermal energy from the unevenly heated region. The system is under the control of a process control computer.
摘要翻译： 一种用于有源阵列温度感测和冷却的系统和方法。 该系统包括有源温度感测层，热电冷却层和散热层。 温度感测层由感测有源阵列基板的不均匀加热区域温度梯度的温度感测元件形成。 热电冷却层控制由感温层感测的温度梯度。 散热层包括用于从不均匀加热的区域吸收热能的多个冷却通道。 该系统由过程控制计算机控制。
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4.发明授权System for and method of forming via holes by use of selective plasma etching in a continuous inline shadow mask deposition process 有权在连续的在线荫罩沉积工艺中通过使用选择性等离子体蚀刻来形成通孔的系统和方法公开(公告)号：US07268431B2
公开(公告)日：2007-09-11
申请号：US11026365
申请日：2004-12-30
IPC分类号： H01L23/52
CPC分类号： C23C14/562 , C23C14/042 , C23C14/5826 , C23C14/5873 , H01L21/76802 , H01L21/76877 , Y10T29/41
摘要： In a shadow mask vapor deposition system, a first conductor is vapor deposited on a substrate and an insulator is vapor deposited on the first conductor. A second conductor is then vapor deposited on at least the insulator. The insulator layer is plasma etched either before or after the vapor deposition of the second conductor to define in the insulator layer a via hole through which at least a portion of the first conductor is exposed. An electrical connection is established between the first and second conductors by way of the via hole.
摘要翻译： 在荫罩气相沉积系统中，将第一导体气相沉积在衬底上，并且在第一导体上蒸镀绝缘体。 然后在至少绝缘体上气相沉积第二导体。 在第二导体的气相沉积之前或之后等离子体蚀刻绝缘体层，以在绝缘体层中限定通孔，第一导体的至少一部分通过该通孔露出。 通过通孔在第一和第二导体之间建立电连接。
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5.发明授权System for and method of planarizing the contact region of a via by use of a continuous inline vacuum deposition 有权通过使用连续在线真空沉积来平坦化通孔的接触区域的系统和方法公开(公告)号：US07361585B2
公开(公告)日：2008-04-22
申请号：US11044140
申请日：2005-01-27
IPC分类号： H01L21/4763 , H01L21/36 , H01L21/20 , H01L21/336
CPC分类号： H01L21/768 , H01L21/6715 , H01L21/67173 , H01L21/67207 , H01L21/76802 , H05K1/0393 , H05K3/143 , H05K3/4076 , H05K3/467 , H05K2201/0179 , H05K2203/1545
摘要： A multi-layer electronic device can be formed to include an insulative substrate (212), a first vapor deposited conductor layer (312) on the insulative substrate (212), a first vapor deposited insulator layer (314) on the first conductor layer (312), the first insulator layer (314) having at least one via hole (316) therein, and a vapor deposited conductive filler (320) in the via hole (316) of the first insulator layer (314). Desirably, the conductive filler (320) is deposited in the via hole (316) of the first insulator layer (314) such that the surface of the conductive filler (320) opposite the first conductor layer (312) is substantially planar with the surface of the first insulator layer (314) opposite the first conductor layer (312).
摘要翻译： 多层电子器件可以形成为在绝缘基板（212）上包括绝缘基板（212），第一蒸镀导体层（312），第一导体层上的第一蒸镀绝缘体层（314） 312），其中具有至少一个通孔（316）的第一绝缘体层（314）和在第一绝缘体层（314）的通孔（316）中的气相沉积导电填料（320）。 期望地，导电填料（320）沉积在第一绝缘体层（314）的通孔（316）中，使得与第一导体层（312）相对的导电填料（320）的表面与表面 与第一导体层（312）相对的第一绝缘体层（314）。
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公开(公告)号：US07271111B2
公开(公告)日：2007-09-18
申请号：US11147508
申请日：2005-06-08
申请人： Thomas P. Brody
发明人： Thomas P. Brody
CPC分类号： H01L27/1288 , C23C14/042 , C23C14/562 , H01L27/1214 , H01L27/14683 , Y10S438/944
摘要： A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.
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公开(公告)号：US4135959A
公开(公告)日：1979-01-23
申请号：US780611
申请日：1977-03-23
申请人： Fang-Chen Luo , Thomas P. Brody
发明人： Fang-Chen Luo , Thomas P. Brody
IPC分类号： G09F13/22 , G09F9/30 , G09G3/20 , G09G3/30 , G09G3/32 , H04N3/14 , H05B33/12 , H05B33/26 , H05B35/00 , B05D5/12
CPC分类号： H04N3/14 , G09G3/32 , G09G2300/0842
摘要： A large area integrated solid-state flat panel display is detailed in which thin film transistor addressing and drive circuitry is provided at each individual picture point with a display medium. The preferred display medium is an electroluminescent phosphor layer. An insulating layer of laminated photoresist is disposed over all electrical circuit elements except the electroluminescent drive electrodes.
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8.发明授权公开(公告)号：US07645708B2
公开(公告)日：2010-01-12
申请号：US11820406
申请日：2007-06-19
申请人： Thomas P. Brody
发明人： Thomas P. Brody
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L27/1288 , C23C14/042 , C23C14/562 , H01L27/1214 , H01L27/14683 , Y10S438/944
摘要： A shadow mask deposition system includes a plurality of identical shadow masks arranged in a number of stacks to form a like number of compound shadow masks, each of which is disposed in a deposition vacuum vessel along with a material deposition source. Materials from the material deposition sources are deposited on the substrate via openings in corresponding compound shadow masks, each opening being formed by the whole or partial alignment of apertures in the shadow masks forming the compound shadow mask, to form an array of electronic elements on the substrate.
摘要翻译： 阴影掩模沉积系统包括多个相同的阴影掩模，其布置在多个堆叠中以形成相同数量的复合荫罩，每个复合荫罩与材料沉积源一起设置在沉积真空容器中。 来自材料沉积源的材料通过相应的复合阴影掩模中的开口沉积在基板上，每个开口由形成复合荫罩的阴影掩模中的孔的整体或部分对准形成，以形成电子元件阵列 基质。
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9.发明授权
公开(公告)号：US5673093A
公开(公告)日：1997-09-30
申请号：US551161
申请日：1995-10-31
申请人： Thomas P. Brody
发明人： Thomas P. Brody
IPC分类号： G02B5/20 , G02F1/1335 , G02F1/1333
CPC分类号： G02B5/201 , G02F1/133516
摘要： A method of producing a color filter to be used in conjunction with a display element such as an active or passive matrix liquid crystal panel. The color filter is formed by a stack of exposed and developed film layers, and each layer corresponds to a color of the resulting filter. The stack of exposed film layers is deposited on a transparent sheet.
摘要翻译： 一种生产与诸如有源或无源矩阵液晶面板的显示元件结合使用的滤色器的方法。 滤色器由曝光和显影的薄膜层的叠层形成，并且每个层对应于所得滤色器的颜色。 曝光的薄膜层堆叠在透明薄片上。
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公开(公告)号：US5352634A
公开(公告)日：1994-10-04
申请号：US855523
申请日：1992-03-23
申请人： Thomas P. Brody
发明人： Thomas P. Brody
IPC分类号： B41F3/34 , B41F17/26 , B41M3/00 , G02F1/1362 , H01L21/027 , H01L21/3213 , H05K3/00 , H05K3/06 , H01L21/302
CPC分类号： B41M3/003 , B41F17/26 , B41F3/34 , H01L21/0273 , H01L21/32139 , H05K3/0079 , G02F1/13454 , H05K3/061 , Y10S438/942
摘要： An improved method of fabricating integrated circuits, particularly active matrix arrays. The present method comprises applying an etch-resist pattern to an integrated circuit by printing to form resist patterns. The circuit is then etched, recoated with a different substance, a new ink pattern applied and the pattern repeated to form the successive layers of the integrated circuit.
摘要翻译： 一种制造集成电路，特别是有源矩阵阵列的改进方法。 本方法包括通过印刷将抗蚀剂图案施加到集成电路以形成抗蚀剂图案。 然后将电路蚀刻，用不同的物质重新涂覆，施加新的油墨图案并重复图案以形成集成电路的连续层。
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