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    Method for writing a large-area closed curvilinear pattern with a cartesian electron beam writing system
    1.
    发明授权
    Method for writing a large-area closed curvilinear pattern with a cartesian electron beam writing system 有权
    用笛卡尔电子束写入系统写入大面积闭合曲线图案的方法

    公开(公告)号：US07525109B2

    公开(公告)日：2009-04-28

    申请号：US11403795

    申请日：2006-04-12

    申请人： Thomas R. Albrecht ,  Zvonimir Bandic ,  Michael J. Rooks

    发明人： Thomas R. Albrecht ,  Zvonimir Bandic ,  Michael J. Rooks

    IPC分类号： H01J37/302

    CPC分类号： H01J37/3026 ,  B82Y10/00 ,  B82Y40/00 ,  G11B5/743 ,  G11B5/82 ,  G11B5/855 ,  H01J37/3174 ,  H01J2237/20228 ,  H01J2237/30438 ,  H01J2237/30455 ,  H01J2237/31764

    摘要： A method for operating a Cartesian-type electron beam (e-beam) lithography (EBL) tool enables the efficient and precise writing of a closed curvilinear pattern, such as a circle, over a wide area of a workpiece. The curvilinear pattern overlies a plurality of contiguous fields of the EBL tool's x-y positioning stage, and the stage is moved along a path defined by the contiguous fields. Alignment marks associated with the first and next-to-last fields are formed on the specimen. The alignment marks are used to adjust the shape of the last field so that when the e-beam is scanned in the last field there is a substantially continuous connection of the pattern between the next-to-last field and the first field. The invention is particularly applicable to making a master disk with concentric circular tracks for nanoimprinting patterned magnetic recording disks.

    摘要翻译： 用于操作笛卡尔电子束（e-beam）光刻（EBL）工具的方法使得能够在工件的广泛区域上有效且精确地写入诸如圆形的闭合曲线图案。 曲线图案覆盖EBL工具的x-y定位台的多个连续的场，并且该台沿着由连续的场定义的路径移动。 在样品上形成与第一和下一个至最后一个场相关联的对准标记。 对准标记用于调整最后一个场的形状，使得当在最后一个场中扫描电子束时，在下一个最后场和第一场之间存在着基本连续的图案连接。 本发明特别适用于制造具有用于纳米压印图案化磁记录盘的同心圆形轨道的母盘。

    A p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors
    5.
    发明申请
    A p-FET with a Strained Nanowire Channel and Embedded SiGe Source and Drain Stressors 有权
    具有应变纳米线通道和嵌入式SiGe源极和漏极应力的p-FET

    公开(公告)号：US20120280211A1

    公开(公告)日：2012-11-08

    申请号：US13554065

    申请日：2012-07-20

    申请人： Guy Cohen ,  Conal E. Murray ,  Michael J. Rooks

    发明人： Guy Cohen ,  Conal E. Murray ,  Michael J. Rooks

    IPC分类号： H01L29/775

    CPC分类号： H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

    摘要： Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

    摘要翻译： 提供了在纳米级基于沟道的场效应晶体管（FET）中嵌入硅锗（e-SiGe）源极和漏极应力的技术。 一方面，制造FET的方法包括以下步骤。 提供其上具有电介质的掺杂衬底。 在电介质上放置至少一个硅（Si）纳米线。 掩模纳米线的一个或多个部分，使纳米线的其它部分暴露出来。 外延锗（Ge）生长在纳米线的暴露部分上。 外延Ge与纳米线中的Si相互扩散以形成纳米线中嵌入纳米线中的压应变的SiGe区域。 掺杂衬底用作FET的栅极，纳米线的掩蔽掉的部分用作FET的沟道，并且嵌入的SiGe区域用作FET的源极和漏极区域。