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    Split gate memory cell using sidewall spacers
    2.
    发明授权
    Split gate memory cell using sidewall spacers 有权
    使用侧壁间隔件的分离栅极存储单元

    公开(公告)号：US07704830B2

    公开(公告)日：2010-04-27

    申请号：US11759518

    申请日：2007-06-07

    申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7881

    摘要： A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.

    摘要翻译： 自对准分离栅极位单元包括由没有电荷存储材料的间隙分开的电荷存储材料的第一和第二区域。 间隔物形成在牺牲层的侧壁上，该牺牲层在位单元堆叠的上方和相对侧上延伸，其中间隔物彼此间隔至少间隙长度。 刻蚀对间隔物有选择性的位单元堆叠形成了将位单元堆叠分成第一和第二栅极的间隙，这些栅极组共同构成了分离栅极位单元堆叠。 比特单元堆叠的存储部分也被蚀刻，其中蚀刻延伸间隙并将相应的层分离成第一和第二分离区域，扩展间隙没有电荷存储材料。 电介质材料沉积在间隙上并被回蚀以暴露牺牲层的顶表面，此牺牲层此后被去除以暴露分裂栅极位晶胞堆叠的侧壁。

    Self-aligned split gate memory cell and method of forming
    3.
    发明授权
    Self-aligned split gate memory cell and method of forming 有权
    自对准分离栅极存储单元及其形成方法

    公开(公告)号：US07528047B2

    公开(公告)日：2009-05-05

    申请号：US11759593

    申请日：2007-06-07

    申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    IPC分类号： H01L21/336

    CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332

    摘要： A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.

    摘要翻译： 使用半导体层形成分离栅极存储器件的方法包括图案化绝缘层以留下其柱。 在半导体层上形成栅极电介质。 电荷存储层形成在栅极电介质上并沿着柱的第一和第二侧。 栅极材料层形成在栅极电介质和支柱上。 执行蚀刻以将栅极材料的第一部分横向邻近柱的第一侧并且位于栅极电介质上方的电荷存储层的第一部分上，以用作存储器件的控制栅极，并且 栅极材料的第二部分横向邻近柱的第二侧，并且位于栅极电介质上方的电荷存储层的第二部分上，用作选择栅极。

    METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SILICON DIOXIDE LAYER
    4.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR DEVICE HAVING A SILICON DIOXIDE LAYER 审中-公开
    形成具有二氧化硅层的半导体器件的方法

    公开(公告)号：US20090061608A1

    公开(公告)日：2009-03-05

    申请号：US11846633

    申请日：2007-08-29

    申请人： Tushar P. Merchant ,  Lakshmanna Vishnubhotla ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Sriram Kalpat

    发明人： Tushar P. Merchant ,  Lakshmanna Vishnubhotla ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Sriram Kalpat

    IPC分类号： H01L21/28

    CPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/66825

    摘要： A method of depositing a silicon dioxide layer for a semiconductor device. The method includes depositing the silicon dioxide layer to have a silicon concentration of greater than 30 atomic percent and a nitrogen concentration of less than 5 atomic percent. The depositing includes flowing nitric oxide gas with a silicon precursor over a substrate. In one example, the silicon precursor and nitric oxide are flowed over a substrate with the substrate being at a temperature in a range of approximately 600 to approximately 900 degrees Celsius. In one example, the silicon dioxide layer is formed on a layer including charge storage memory material.

    摘要翻译： 一种沉积半导体器件的二氧化硅层的方法。 该方法包括沉积二氧化硅层以具有大于30原子百分比的硅浓度和小于5原子％的氮浓度。 沉积包括在衬底上流动具有硅前体的一氧化氮气体。 在一个实例中，硅前体和一氧化氮在衬底上流动，衬底的温度在约600至约900摄氏度的范围内。 在一个示例中，二氧化硅层形成在包括电荷存储存储材料的层上。

    SELF-ALIGNED SPLIT GATE MEMORY CELL AND METHOD OF FORMING
    5.
    发明申请
    SELF-ALIGNED SPLIT GATE MEMORY CELL AND METHOD OF FORMING 有权
    自对准的分离栅格存储单元和形成方法

    公开(公告)号：US20080303094A1

    公开(公告)日：2008-12-11

    申请号：US11759593

    申请日：2007-06-07

    申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    IPC分类号： H01L29/78 ,  H01L21/04 ,  H01L29/68

    CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42332

    摘要： A method of forming a split gate memory device using a semiconductor layer includes patterning an insulating layer to leave a pillar thereof. A gate dielectric is formed over the semiconductor layer. A charge storage layer is formed over the gate dielectric and along first and second sides of the pillar. A gate material layer is formed over the gate dielectric and pillar. An etch is performed to leave a first portion of the gate material laterally adjacent to a first side of the pillar and over a first portion of the charge storage layer that is over the gate dielectric to function as a control gate of the memory device and a second portion of the gate material laterally adjacent to a second side of the pillar and over a second portion of the charge storage layer that is over the gate dielectric to function as a select gate.

    摘要翻译： 使用半导体层形成分离栅极存储器件的方法包括图案化绝缘层以留下其柱。 在半导体层上形成栅极电介质。 电荷存储层形成在栅极电介质上并沿着柱的第一和第二侧。 栅极材料层形成在栅极电介质和支柱上。 执行蚀刻以将栅极材料的第一部分横向邻近柱的第一侧并且位于栅极电介质上方的电荷存储层的第一部分上，以用作存储器件的控制栅极，并且 栅极材料的第二部分横向邻近柱的第二侧，并且位于栅极电介质上方的电荷存储层的第二部分上，用作选择栅极。

    SPLIT GATE MEMORY CELL USING SIDEWALL SPACERS
    6.
    发明申请
    SPLIT GATE MEMORY CELL USING SIDEWALL SPACERS 有权
    分离栅格存储单元使用边框间隔

    公开(公告)号：US20080303067A1

    公开(公告)日：2008-12-11

    申请号：US11759518

    申请日：2007-06-07

    申请人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    发明人： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar ,  Lakshmanna Vishnubhotla

    IPC分类号： H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/7881

    摘要： A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.

    摘要翻译： 自对准分离栅极位单元包括由没有电荷存储材料的间隙分开的电荷存储材料的第一和第二区域。 间隔物形成在牺牲层的侧壁上，该牺牲层在位单元堆叠的上方和相对侧上延伸，其中间隔物彼此间隔至少间隙长度。 刻蚀对间隔物有选择性的位单元堆叠形成了将位单元堆叠分成第一和第二栅极的间隙，这些栅极组共同构成了分离栅极位单元堆叠。 比特单元堆叠的存储部分也被蚀刻，其中蚀刻延伸间隙并将相应的层分离成第一和第二分离区域，扩展间隙没有电荷存储材料。 电介质材料沉积在间隙上并被回蚀以暴露牺牲层的顶表面，此牺牲层此后被去除以暴露分裂栅极位晶胞堆叠的侧壁。