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    SILICON WAFER THINNING END POINT METHOD
    1.
    发明申请
    SILICON WAFER THINNING END POINT METHOD 有权
    硅氧化薄点法

    公开(公告)号：US20080124896A1

    公开(公告)日：2008-05-29

    申请号：US11563715

    申请日：2006-11-28

    Applicant: Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

    Inventor： Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

    IPC: H01L21/461

    CPC classification number: H01L21/78

    Abstract: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.

    Abstract translation: 公开了用于制造半导体晶片的方法和系统。 该方法包括以下步骤：提供具有正面和背面的硅晶片，在晶片前侧构建集成电路，然后从硅晶片的背面去除衬底。 构建步骤包括以下步骤：在晶片中形成期望的结构，并且在晶片中形成端部结构，所述端部结构延伸到比晶片的背面更大的深度，而不是期望的结构。 此外，除去步骤包括仅将该基材除去至端部结构的步骤，由此在除去步骤期间不除去所需结构的一部分。

    Method for thinning wafers that have contact bumps
    2.
    发明授权
    Method for thinning wafers that have contact bumps 失效
    稀释具有接触凸点的晶片的方法

    公开(公告)号：US07135124B2

    公开(公告)日：2006-11-14

    申请号：US10713659

    申请日：2003-11-13

    Applicant: Timothy C. Krywanczyk ,  Edmund J. Sprogis

    Inventor： Timothy C. Krywanczyk ,  Edmund J. Sprogis

    IPC: H01L21/302 ,  C23F1/00 ,  B24B1/00

    CPC classification number: H01L21/78

    Abstract: In accordance with the foregoing objects and advantages, the present invention provides a fabrication device that may be used during the grinding operation of the fabrication process. The fabrication device comprises a socket plate that includes a plurality of cavities formed therein that correspond in position and number to the solder (or other conductive material) bumps formed on the front surface of a product wafer.

    Abstract translation: 根据上述目的和优点，本发明提供了可在制造过程的磨削操作期间使用的制造装置。 该制造装置包括插座板，该插座板包括形成在其中的多个空腔，其位置和数量与形成在产品晶片的前表面上的焊料（或其他导电材料）凸起相对应。

    Silicon wafer thinning end point method
    8.
    发明授权
    Silicon wafer thinning end point method 有权
    硅晶片薄化端点法

    公开(公告)号：US07498236B2

    公开(公告)日：2009-03-03

    申请号：US11563715

    申请日：2006-11-28

    Applicant: Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

    Inventor： Steven R. Codding ,  Timothy C. Krywanczyk ,  Edmund J. Sprogis

    IPC: H01L21/30 ,  H01L21/46 ,  H01L21/306 ,  C23F1/00

    CPC classification number: H01L21/78

    Abstract: Disclosed are a method of and system for fabricating a semiconductor wafer. The method comprises the steps of providing a silicon wafer having a front side an a back side, building an integrated circuit on the front side of the wafer, and thereafter removing substrate from the back side of the silicon wafer. The building step includes the steps of forming a desired structure in the wafer, and forming an end structure in the wafer, said end structure extending to a greater depth, toward the back side of the wafer, than the desired structure. Also, the removing step includes the step of removing said substrate only to the end structure, whereby no part of the desired structure is removed during the removing step.

    Abstract translation: 公开了用于制造半导体晶片的方法和系统。 该方法包括以下步骤：提供具有正面和背面的硅晶片，在晶片前侧构建集成电路，然后从硅晶片的背面去除衬底。 构建步骤包括以下步骤：在晶片中形成期望的结构，并且在晶片中形成端部结构，所述端部结构延伸到比晶片的背面更大的深度，而不是期望的结构。 此外，除去步骤包括仅将该基材除去至端部结构的步骤，由此在除去步骤期间不除去所需结构的一部分。

    Coil inductor for on-chip or on-chip stack
    10.
    发明授权
    Coil inductor for on-chip or on-chip stack 有权
    用于片上或片上堆叠的线圈电感

    公开(公告)号：US09105627B2

    公开(公告)日：2015-08-11

    申请号：US13289071

    申请日：2011-11-04

    Applicant: Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    Inventor： Michael J. Shapiro ,  Gary D. Carpenter ,  Alan J. Drake ,  Rachel Gordin ,  Edmund J. Sprogis

    IPC: H01F5/00 ,  H01L27/08 ,  H01L23/498 ,  H01L23/522 ,  H01L23/64 ,  H01L49/02 ,  H01F17/00 ,  H01F41/00

    CPC classification number: H01L23/49822 ,  H01F17/0013 ,  H01F41/005 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L23/645 ,  H01L28/10 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/00

    Abstract: A coil inductor and buck voltage regulator incorporating the coil inductor are provided which can be fabricated on a microelectronic element such as a semiconductor chip, or on an interconnection element such as a semiconductor, glass or ceramic interposer element. When energized, the coil inductor has magnetic flux extending in a direction parallel to first and second opposed surfaces of the microelectronic or interconnection element, and whose peak magnetic flux is disposed between the first and second surfaces. In one example, the coil inductor can be formed by first conductive lines extending along the first surface of the microelectronic or interconnection element, second conductive lines extending along the second surface of the microelectronic or interconnection element, and a plurality of conductive vias, e.g., through silicon vias, extending in direction of a thickness of the microelectronic or interconnection element. A method of making the coil inductor is also provided.

    Abstract translation: 提供了一种结合线圈电感器的线圈电感器和降压稳压器，其可以制造在诸如半导体芯片的微电子元件上，或者在诸如半导体，玻璃或陶瓷插入元件的互连元件上。 当通电时，线圈电感器具有沿平行于微电子或互连元件的第一和第二相对表面的方向延伸的磁通量，并且其峰值磁通量设置在第一和第二表面之间。 在一个示例中，线圈电感器可以由沿着微电子或互连元件的第一表面延伸的第一导线形成，沿着微电子或互连元件的第二表面延伸的第二导电线，以及多个导电通孔， 通过硅通孔，在微电子或互连元件的厚度方向上延伸。 还提供了制造线圈电感器的方法。

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