公开(公告)号：US08148248B2

公开(公告)日：2012-04-03

申请号：US13053733

申请日：2011-03-22

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US20070077736A1

公开(公告)日：2007-04-05

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/04

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US06407419B1

公开(公告)日：2002-06-18

申请号：US09362669

申请日：1999-07-29

申请人： Tomonori Okudaira

发明人： Tomonori Okudaira

IPC分类号： H01L27108

CPC分类号： H01L27/11502 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76888 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/11507 ,  H01L28/40

摘要： A semiconductor device preventing contact between a capacitor insulator and a plug material even when an upper surface of the plug is exposed by misregistration in lithography and manufacturing method thereof are obtained. The semiconductor device includes an interlayer insulating film, a conducting plug, a capacitor lower electrode and a capacitor dielectric, and an end portion of the upper surface of the conducting plug has a portion overlapping a vicinity of an outer periphery of the upper surface of the capacitor lower electrode when viewed two-dimensionally. In the vicinity of the end portion of the upper surface of the conducting plug, a chemically inactive member is formed.

摘要翻译： 即使当在光刻中通过不对准露出插头的上表面时，也可以防止电容器绝缘体和插塞材料之间的接触的半导体器件及其制造方法。 半导体器件包括层间绝缘膜，导电插塞，电容器下电极和电容器电介质，并且导电插塞的上表面的端部具有与所述导电插塞的上表面的外周附近重叠的部分 电容器下电极二维观察。 在导电塞的上表面的端部附近形成化学惰性部件。

公开(公告)号：US06078072A

公开(公告)日：2000-06-20

申请号：US73834

申请日：1998-05-06

申请人： Tomonori Okudaira ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L29/76 ,  H01L27/108 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L27/10852 ,  H01L28/60 ,  H01L28/55

摘要： A lower electrode layer 1 of a capacitor 10 is formed by sputtering performed at a temperature lower than 450.degree. C. in an atmosphere containing oxygen, and thereby the lower electrode layer 1 thus formed contains oxygen. Thereby, a method of manufacturing a semiconductor device having the capacitor can suppress current leak, and can prevent peeling of an electrode.

摘要翻译： 电容器10的下电极层1通过在低于450℃的温度下在含氧气氛中进行溅射而形成，由此形成的下电极层1含有氧。 因此，制造具有电容器的半导体器件的方法可以抑制电流泄漏，并且可以防止电极的剥离。

公开(公告)号：US06033732A

公开(公告)日：2000-03-07

申请号：US70009

申请日：1998-04-30

申请人： Akimasa Yuuki ,  Takaaki Kawahara ,  Tetsuro Makita ,  Mikio Yamamuka ,  Koichi Ono ,  Tomonori Okudaira

发明人： Akimasa Yuuki ,  Takaaki Kawahara ,  Tetsuro Makita ,  Mikio Yamamuka ,  Koichi Ono ,  Tomonori Okudaira

IPC分类号： C23C16/40 ,  C23C16/448 ,  C23C16/52 ,  C23C16/54 ,  C23C14/08

CPC分类号： C23C16/409 ,  C23C16/4481 ,  C23C16/52 ,  C23C16/54

摘要： A method of depositing a thin film on a substrate by chemical vapor deposition (CVD) including feeding a liquid CVD source material, including a solution in which at least one organometallic complex is dissolved in a solvent, at a constant flow rate to a vaporizer while keeping the CVD source material in a liquid state; vaporizing the liquid CVD source material by heating to form a CVD source material gas; and forming a thin film of a metal oxide on a substrate using the CVD material source gas in a reaction chamber, the thin film including at least titanium, including using TTIP and TiO(Dpm).sub.2 together as the organometallic complex.

摘要翻译： 一种通过化学气相沉积（CVD）在衬底上沉积薄膜的方法，包括将恒定流速的液态CVD源材料（包括其中至少一种有机金属配合物溶解在溶剂中）的溶液进料到蒸发器，同时 保持CVD源材料处于液态; 通过加热蒸发液体CVD源材料以形成CVD源材料气体; 以及使用所述CVD材料源气体在反应室中在基板上形成金属氧化物薄膜，所述薄膜至少包括钛，包括使用TTIP和TiO（Dpm）2作为有机金属络合物。

公开(公告)号：US5776254A

公开(公告)日：1998-07-07

申请号：US579495

申请日：1995-12-27

申请人： Akimasa Yuuki ,  Takaaki Kawahara ,  Tetsuro Makita ,  Mikio Yamamuka ,  Koichi Ono ,  Tomonori Okudaira

发明人： Akimasa Yuuki ,  Takaaki Kawahara ,  Tetsuro Makita ,  Mikio Yamamuka ,  Koichi Ono ,  Tomonori Okudaira

IPC分类号： C23C16/40 ,  C23C16/448 ,  C23C16/52 ,  C23C16/54 ,  C23C16/00

CPC分类号： C23C16/409 ,  C23C16/4481 ,  C23C16/52 ,  C23C16/54

摘要： A chemical vapor deposition (CVD) apparatus for depositing a thin film on a substrate by CVD has a material container for containing a liquid CVD source material, a material feeder for feeding the liquid CVD source material to a vaporizer for vaporizing the liquid CVD source material, and a reaction chamber for forming the thin film on the substrate using the CVD source material gas. Both the vaporizer and piping between the vaporizer and the reaction chamber are located in a thermostatic box surrounding the reaction chamber. Thus, the structure of the apparatus is simplified and also the heat efficiency of the apparatus is improved.

摘要翻译： 用于通过CVD在基板上沉积薄膜的化学气相沉积（CVD）装置具有用于容纳液体CVD源材料的材料容器，用于将液体CVD源材料供给到用于使液体CVD源材料蒸发的蒸发器的材料供料器 以及用于使用CVD源材料气体在基板上形成薄膜的反应室。 蒸发器和反应室之间的蒸发器和管道都位于围绕反应室的恒温箱中。 因此，简化了装置的结构，提高了装置的热效率。

公开(公告)号：US5218219A

公开(公告)日：1993-06-08

申请号：US678872

申请日：1991-04-04

申请人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Natsuo Ajika ,  Hideaki Arima ,  Kaoru Motonami ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10817

摘要： A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

摘要翻译： 公开了一种动态随机存取存储器（DRAM），其即使在高集成器件中也能够有效地防止存储单元阵列101和外围电路102的边界区域中的步骤的形成。 该DRAM包括在存储单元阵列101的边界区域和P型硅衬底1的外围电路102的外围壁20a和20b的双周壁20，P型硅衬底1从P型硅衬底1垂直向上延伸。 形成在存储单元阵列上的器件的表面和外围电路102在存储单元阵列101和外围电路102上的形成装置中通过双周壁20的病毒基本平坦化，从而有效地防止了在步骤 存储单元阵列101和外围电路102的边界区域，即使在高集成器件中。

公开(公告)号：US20100171183A1

公开(公告)日：2010-07-08

申请号：US12727334

申请日：2010-03-19

申请人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L27/092

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US20080121950A1

公开(公告)日：2008-05-29

申请号：US11771340

申请日：2007-06-29

申请人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi YAMAGUCHI ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7848

摘要： Even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is realized.The channel length direction of n channel MISFET where the silicide region of nickel or a nickel alloy was formed on the source and the drain is arranged so that it may become parallel to the crystal orientation of a semiconductor substrate. Since it is hard to extend the silicide region of nickel or a nickel alloy in the direction of crystal orientation , even if it is a case where the silicide region of nickel or a nickel alloy is formed in the source and drain of n channel MISFET, the semiconductor device in which OFF leakage current does not increase easily is obtained.

摘要翻译： 即使是在n沟道MISFET的源极和漏极中形成镍或镍合金的硅化物区域的情况，也可以实现OFF泄漏电流容易增加的半导体器件。 在源极和漏极上形成镍或镍合金的硅化物区域的n沟道MISFET的沟道长度方向被布置成使其可以平行于半导体衬底的晶体取向<100>。 由于难以在晶体取向<100>的方向上延伸镍或镍合金的硅化物区域，所以即使在镍或镍合金的硅化物区域形成在n的源极和漏极中的情况 通道MISFET，可以容易地提高OFF漏电流的半导体装置。

公开(公告)号：US5753527A

公开(公告)日：1998-05-19

申请号：US613555

申请日：1996-03-11

申请人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

发明人： Hiromi Itoh ,  Tomonori Okudaira ,  Keiichiro Kashihara

IPC分类号： H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10808

摘要： A first interlayer insulating film having a second contact hole is formed on a main surface of a semiconductor substrate 1 in a peripheral circuitry. A second plug electrode of the same material as a first plug electrode in a memory cell array is formed in the second contact hole. A pad layer is formed over the second plug electrode and a top surface of the first interlayer insulating film. The pad layer and a capacitor lower electrode are made of the same material. The pad layer is covered with the second interlayer insulating film. A third contact hole is formed at a portion of the second interlayer insulating film located above the pad layer. A first aluminum interconnection layer is formed in the third contact hole. Thereby, a contact can be formed easily between the interconnection layer and the main surface of the semiconductor substrate in the peripheral circuitry of a DRAM, and a manufacturing process can be simplified.

摘要翻译： 具有第二接触孔的第一层间绝缘膜形成在外围电路中的半导体衬底1的主表面上。 在第二接触孔中形成有与存储单元阵列中的第一插头电极相同材料的第二插头电极。 在第二插头电极和第一层间绝缘膜的顶表面上形成衬垫层。 焊盘层和电容器下电极由相同的材料制成。 衬垫层被第二层间绝缘膜覆盖。 在位于焊盘层上方的第二层间绝缘膜的一部分处形成第三接触孔。 在第三接触孔中形成第一铝互连层。 因此，可以在DRAM的外围电路中的互连层和半导体衬底的主表面之间容易地形成接触，并且可以简化制造工艺。