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62 条记录 (耗时 0.024 秒)

    Method for formation of insulation film on silicon buried in trench
    1.
    发明授权
    Method for formation of insulation film on silicon buried in trench 失效
    在埋在沟槽中的硅上形成绝缘膜的方法

    公开(公告)号：US4873203A

    公开(公告)日：1989-10-10

    申请号：US221351

    申请日：1988-07-19

    申请人： Toru Kaga ,  Shinichiro Kimura ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Hideo Sunami

    发明人： Toru Kaga ,  Shinichiro Kimura ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Hideo Sunami

    IPC分类号： H01L27/04 ,  H01L21/316 ,  H01L21/32 ,  H01L21/334 ,  H01L21/763 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L29/66181 ,  H01L21/32 ,  H01L21/763

    摘要： An insulation film on silicon buried in a trench is prepared by forming a field oxide film by using a first Si.sub.3 N.sub.4 mask formed on a silicon substrate, forming a second Si.sub.3 N.sub.4 mask for formation of a trench, forming a trench in the silicon substrate by using the second Si.sub.3 N.sub.4 mask, burying polycrystalline silicon in the trench, removing the second Si.sub.3 N.sub.4 mask while leaving the first Si.sub.3 N.sub.4 mask and oxidizing the surface of the polycrystalline silicon buried in the trench by thermal oxidation. The so-formed insulation film on silicon buried in the trench has a uniform thickness and a high dielectric strength. The surface of the substrate at a part where an active element will be formed in the future is not oxidized.

    摘要翻译： 通过使用在硅衬底上形成的第一Si 3 N 4掩模形成场氧化膜，形成用于形成沟槽的第二Si 3 N 4掩模，通过使用硅衬底形成硅衬底中的沟槽来制备掩埋在沟槽中的硅上的绝缘膜 第二Si 3 N 4掩模，在沟槽中埋入多晶硅，除去第二Si 3 N 4掩模，同时留下第一Si 3 N 4掩模，并通过热氧化氧化掩埋在沟槽中的多晶硅的表面。 埋在沟槽中的硅上如此形成的绝缘膜具有均匀的厚度和高介电强度。 在将来将形成有源元件的部分处的基板的表面不被氧化。

    Method of fabricating stacked capacitor cell memory devices
    2.
    发明授权
    Method of fabricating stacked capacitor cell memory devices 失效
    叠层电容器单元存储器件的制造方法

    公开(公告)号：US5374576A

    公开(公告)日：1994-12-20

    申请号：US72482

    申请日：1993-06-03

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L21/265 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device
    3.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US06878586B2

    公开(公告)日：2005-04-12

    申请号：US10458271

    申请日：2003-06-11

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45 ,  H01L21/8242

    CPC分类号： H01L27/10817 ,  H01L27/10808 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device
    5.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5591998A

    公开(公告)日：1997-01-07

    申请号：US443106

    申请日：1995-05-17

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device having stacked capacitors
    6.
    发明授权
    Semiconductor memory device having stacked capacitors 失效
    具有层叠电容器的半导体存储器件

    公开(公告)号：US5583358A

    公开(公告)日：1996-12-10

    申请号：US324352

    申请日：1994-10-17

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108 ,  H01L29/417 ,  H01L29/45

    CPC分类号： H01L27/10808 ,  H01L27/10817 ,  H01L29/41775 ,  H01L29/456

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储容量 部分布置非常密集，并且具有足够大的容量以保持非常小的单元格区域。 由于存储容量部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的容量减小，因此存储器阵列噪声减小。 也可以设计电荷存储容量部分，使得其一部分具有基本上垂直于衬底的壁的形式，以增加容量。

    Semiconductor memory device having stacked capacitor cells
    7.
    发明授权
    Semiconductor memory device having stacked capacitor cells 失效
    具有层叠电容器单元的半导体存储器件

    公开(公告)号：US5140389A

    公开(公告)日：1992-08-18

    申请号：US475148

    申请日：1990-02-05

    申请人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    发明人： Shinichiro Kimura ,  Naotaka Hashimoto ,  Yoshio Sakai ,  Tokuo Kure ,  Yoshifumi Kawamoto ,  Toru Kaga ,  Eiji Takeda

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10817

    摘要： A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.

    摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45度的角度倾斜，从而使得存储电容器 要非常密集地布置的部分和足够大的电容以保持非常小的电池区域。 由于存储电容器部分甚至在位线上形成，所以位线被屏蔽，使得位线之间的电容减小，因此存储器阵列噪声减小。 也可以设计电荷存储电容器部分，使得其一部分呈基本上垂直于衬底的壁的形式，以增加电容。

    Method for fabricating semiconductor memory with a groove
    8.
    发明授权
    Method for fabricating semiconductor memory with a groove 失效
    用于制造具有凹槽的半导体存储器的方法

    公开(公告)号：US06355517B1

    公开(公告)日：2002-03-12

    申请号：US08172101

    申请日：1993-12-23

    申请人： Hideo Sunami ,  Tokuo Kure ,  Yoshifumi Kawamoto

    发明人： Hideo Sunami ,  Tokuo Kure ,  Yoshifumi Kawamoto

    IPC分类号： H01L218242

    CPC分类号： G11C11/404 ,  H01L27/10829

    摘要： A semiconductor memory having a capacitor formed by utilizing a groove formed in a semiconductor substrate and an insulated gate field effect transistor and suppressing expansion of a depletion layer from the groove, and a method for fabricating the same are disclosed. An area occupied by each memory cell can be made very small and a distance between the memory cells can also be made very small, accordingly, high density integration is facilitated.

    摘要翻译： 公开了一种半导体存储器，其具有通过利用形成在半导体衬底中的沟槽和绝缘栅场效应晶体管而形成的电容器，并且抑制了耗尽层从沟槽的膨胀及其制造方法。 可以使每个存储单元所占据的面积非常小，并且存储单元之间的距离也可以非常小，因此便于高密度集成。