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    Semiconductor device and method for manufacturing the same
    3.
    发明申请
    Semiconductor device and method for manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060121714A1

    公开(公告)日：2006-06-08

    申请号：US11103562

    申请日：2005-04-12

    申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi ,  Toshifumi Mori

    发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi ,  Toshifumi Mori

    IPC分类号： H01L21/3205

    CPC分类号： H01L21/02115 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/28518 ,  H01L21/3145 ,  H01L21/76837 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： Disclosed is a method for manufacturing a semiconductor device provided with a sidewall having a high quality and an excellent shape. The sidewall on a gate electrode side wall is formed using a carbon-containing silicon nitride oxide film. The film can be formed by a CVD method using, as starting materials, BTBAS and oxygen where a BTBAS flow rate/oxygen flow rate ratio is appropriately set and a low film formation temperature is set, for example, at about 530° C. When forming the sidewall using this film, improvement in HF resistance and reduction in fringe capacitance can be realized due to contribution of nitrogen atoms and carbon atoms. Further, when forming this film under low temperature conditions, unnecessary diffusion of impurities introduced into a semiconductor substrate can be suppressed. Thus, transistor characteristics are enhanced and stabilized, so that high performance and high quality in the semiconductor device can be realized.

    摘要翻译： 公开了一种具有高质量和优良形状的侧壁的半导体器件的制造方法。 栅电极侧壁上的侧壁使用含碳氮氧化硅膜形成。 可以通过使用BTBAS和氧气作为原料的BTBAS流量/氧气流量比适当设定并且低成膜温度设定为例如约530℃的CVD法形成。当 使用该膜形成侧壁，由于氮原子和碳原子的贡献，可以实现HF电阻的提高和边缘电容的降低。 此外，当在低温条件下形成该膜时，可以抑制引入到半导体衬底中的杂质的不必要的扩散。 因此，晶体管特性得到增强和稳定，从而可以实现半导体器件的高性能和高质量。

    Semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate
    5.
    发明授权
    Semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate 有权
    在侧壁绝缘膜和半导体衬底之间具有缓冲层的半导体器件

    公开(公告)号：US07906798B2

    公开(公告)日：2011-03-15

    申请号：US11950102

    申请日：2007-12-04

    申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    IPC分类号： H01L27/092

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

    摘要翻译： 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

    Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate
    6.
    发明授权
    Method of forming semiconductor device having buffer layer between sidewall insulating film and semiconductor substrate 有权
    在侧壁绝缘膜和半导体衬底之间形成具有缓冲层的半导体器件的方法

    公开(公告)号：US08481383B2

    公开(公告)日：2013-07-09

    申请号：US13024988

    申请日：2011-02-10

    申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    IPC分类号： H01L21/8238 ,  H01L27/092

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

    摘要翻译： 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    半导体器件及制造半导体器件的方法

    公开(公告)号：US20080142838A1

    公开(公告)日：2008-06-19

    申请号：US11950102

    申请日：2007-12-04

    申请人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    发明人： Hiroyuki Ohta ,  Katsuaki Ookoshi

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L21/823864 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

    摘要： A semiconductor device includes an NMOS transistor and a PMOS transistor. The NMOS transistor includes a channel area formed in a silicon substrate, a gate electrode formed on a gate insulating film in correspondence with the channel area, and a source area and a drain area formed in the silicon substrate having the channel area situated therebetween. The PMOS transistor includes another channel area formed in the silicon substrate, another gate electrode formed on another gate insulating film in correspondence with the other channel area, and another source area and another drain area formed in the silicon substrate having the other channel area situated therebetween. The gate electrode has first sidewall insulating films. The other gate electrode has second sidewall insulating films. The distance between the second sidewall insulating films and the silicon substrate is greater than the distance between the first sidewall insulating films and the silicon substrate.

    摘要翻译： 半导体器件包括NMOS晶体管和PMOS晶体管。 NMOS晶体管包括形成在硅衬底中的沟道区，形成在与沟道区相对应的栅极绝缘膜上的栅电极，以及形成在硅衬底中的沟道区的源极区和漏区，位于其间。 PMOS晶体管包括形成在硅衬底中的另一沟道区，与另一沟道区相对应的另一栅极电极上形成的另一栅电极，以及形成在硅衬底中的另一源极区和另一漏极区，其另一沟道区位于其间 。 栅电极具有第一侧壁绝缘膜。 另一个栅电极具有第二侧壁绝缘膜。 第二侧壁绝缘膜和硅衬底之间的距离大于第一侧壁绝缘膜和硅衬底之间的距离。

    Manufacture of semiconductor device having STI and semiconductor device manufactured
    9.
    发明授权
    Manufacture of semiconductor device having STI and semiconductor device manufactured 有权
    制造具有STI和半导体器件的半导体器件的制造

    公开(公告)号：US07037803B2

    公开(公告)日：2006-05-02

    申请号：US10721870

    申请日：2003-11-26

    申请人： Kengo Inoue ,  Toshifumi Mori ,  Ryou Nakamura ,  Hiroyuki Ohta ,  Takashi Saiki

    发明人： Kengo Inoue ,  Toshifumi Mori ,  Ryou Nakamura ,  Hiroyuki Ohta ,  Takashi Saiki

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76224 ,  H01L21/823871 ,  H01L21/823878

    摘要： A semiconductor device manufacture method has the steps of: (a) forming a polishing stopper layer over a semiconductor substrate; (b) etching the semiconductor substrate to form a trench; (c) forming a first liner insulating layer of silicon oxide over the surface of the trench; (d) forming a second liner insulating layer of silicon nitride over the first liner insulating layer, the second liner insulating layer having a thickness of at least 20 nm or at most 8 nm; (e1) depositing a third liner insulating layer of silicon oxide over the second liner insulating layer by plasma CVD at a first bias; and (e2) depositing an isolation layer of silicon oxide by plasma CVD at a second bias higher than the first bias, the isolation layer burying a recess defined by the third liner insulating layer.

    摘要翻译： 半导体器件制造方法具有以下步骤：（a）在半导体衬底上形成抛光阻挡层; （b）蚀刻半导体衬底以形成沟槽; （c）在所述沟槽的表面上形成氧化硅的第一衬垫绝缘层; （d）在所述第一衬垫绝缘层上形成氮化硅的第二衬垫绝缘层，所述第二衬垫绝缘层的厚度为至少20nm或至多8nm; （e1）在第一偏压下通过等离子体CVD沉积第二衬里绝缘层上的第三衬垫绝缘层氧化硅; 和（e2）以高于第一偏压的第二偏压通过等离子体CVD沉积氧化硅隔离层，隔离层埋设由第三衬里绝缘层限定的凹部。