公开(公告)号：US5611057A

公开(公告)日：1997-03-11

申请号：US376312

申请日：1995-01-20

申请人： Victor K. Pecone ,  Russell C. Smith ,  Jay R. Lory

发明人： Victor K. Pecone ,  Russell C. Smith ,  Jay R. Lory

IPC分类号： G06F1/18 ,  H05K1/00 ,  H05K1/14 ,  H01R23/00

CPC分类号： G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  H05K1/0286 ,  H05K1/141

摘要： A daughter card for mounting to an adapter card, wherein the daughter card includes adapter card connectors for mounting to the adapter card and also an edge connector for insertion directly into a computer slot so that the daughter card may also function as a stand-alone card. The daughter card is both mechanically and electrically compliant as an independent PCI add-in card and includes a PCI edge connector for insertion directly into a PCI slot. This provides additional modularity since the daughter card can be purchased and configured as a separate and independent PCI adapter card as well as for mating to a host adapter card to provide extra functionality to the host adapter card. In addition, since the daughter card can be directly inserted into the PCI bus, the daughter card provides greater component access and probing for testing. Further, the daughter card can be tested independently of the host adapter card during manufacturing functional test, thus providing more reliable testing.

摘要翻译： 用于安装到适配卡的子卡，其中子卡包括用于安装到适配器卡的适配器卡连接器以及用于直接插入到计算机插槽中的边缘连接器，使得子卡还可以用作独立卡 。 子卡作为独立的PCI附加卡机械和电气兼容，并且包括用于直接插入PCI插槽的PCI边缘连接器。 这提供了额外的模块化，因为子卡可以被购买并被配置为单独的和独立的PCI适配器卡，以及用于与主机适配器卡匹配以向主机适配器卡提供额外的功能。 此外，由于子卡可以直接插入到PCI总线中，子卡提供了更大的组件访问和探测来进行测试。 此外，在制造功能测试期间，子卡可以独立于主机适配器卡进行测试，从而提供更可靠的测试。

公开(公告)号：US5768622A

公开(公告)日：1998-06-16

申请号：US516837

申请日：1995-08-18

申请人： Jay R. Lory ,  Victor K. Pecone

发明人： Jay R. Lory ,  Victor K. Pecone

IPC分类号： G06F13/42 ,  G06F13/28

CPC分类号： G06F13/423

摘要： A PCI bus master which determines the termination characteristics of one or more PCI targets coupled to the bus and uses this information to eliminate the wait states that are incurred during a bus cycle when a target device attempts to perform a data phase termination. According to the present invention, at initialization the bus master performs burst cycles on arbitrary address boundaries and stores the target's termination boundaries and cycle conditions. The bus master uses this information during burst transfers to initiate the data phase termination prior to the target, thus preempting the target from performing this termination. This operates to maintain the target's maximum burst capabilities while also eliminating the rearbitration wait states incurred when the bus master receives a termination from the target device. This also allows the bus master to chain together fast back-to-back PCI cycles while retaining bus ownership.

摘要翻译： PCI总线主机，其确定耦合到总线的一个或多个PCI目标的终止特性，并使用该信息来消除当目标设备尝试执行数据相位终止时在总线周期期间产生的等待状态。 根据本发明，在初始化时，总线主机在任意地址边界上执行突发周期，并存储目标的终止边界和周期条件。 总线主机在突发传输期间使用该信息以在目标之前启动数据相位终止，从而抢占目标执行该终止。 这样做可以保持目标的最大突发能力，同时消除总线主机从目标设备接收终端时引起的后台等待状态。 这也允许总线主机在保持总线所有权的同时将快速背靠背PCI循环链接在一起。

公开(公告)号：US5933616A

公开(公告)日：1999-08-03

申请号：US895661

申请日：1997-07-17

申请人： Victor K. Pecone ,  Jay R. Lory

发明人： Victor K. Pecone ,  Jay R. Lory

IPC分类号： G06F13/364 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40

CPC分类号： G06F13/364

摘要： A computer system is provided wherein a bus master generates a signal indicative of the type of cycle it plans to initiate when requesting bus ownership. Other bus masters may be configured to generate similar cycle-type signals. A bus arbiter samples each master's unique cycle type signal during the request phase, and further receives information regarding the status of various target resources. Based upon the cycle type signals from requesting masters and upon the target resource information, the bus arbiter determines whether a master is planning to access an unavailable target resource. A master that is planning to access an unavailable target resource will be denied access of the bus. Accordingly, other masters intending to initiate cycles to available target resources may be granted ownership of the bus. As a result, target termination retry cycles may be avoided, and bus bandwidth and overall system performance may be improved.

摘要翻译： 提供了一种计算机系统，其中总线主机产生指示在请求总线所有权时计划启动的周期类型的信号。 其他总线主机可以被配置为产生类似的循环型信号。 总线仲裁器在请求阶段对每个主机的独特周期类型信号进行采样，并进一步接收关于各种目标资源状态的信息。 基于来自请求主机的周期类型信号和目标资源信息，总线仲裁器确定主机是否计划访问不可用的目标资源。 计划访问不可用的目标资源的主机将被拒绝访问总线。 因此，其他想要向现有目标资源启动周期的主人可以被授予公共汽车的所有权。 因此，可以避免目标终止重试周期，并且可以提高总线带宽和总体系统性能。

公开(公告)号：US5567295A

公开(公告)日：1996-10-22

申请号：US180175

申请日：1994-01-11

申请人： Deepak N. Swamy ,  Victor K. Pecone

发明人： Deepak N. Swamy ,  Victor K. Pecone

IPC分类号： C07K14/71 ,  G01N33/566 ,  G01N33/74 ,  H05K1/11 ,  H05K3/00 ,  H05K3/24 ,  C25D5/02

CPC分类号： H05K3/242 ,  C25D17/005 ,  H05K1/117 ,  H05K2201/094 ,  H05K2203/175 ,  H05K3/0047 ,  H05K3/0052

摘要： An inexpensive method for fabricating a staggered edge connector for a circuit board. The method is cost effective and includes numerous advantages over the prior art, including allowing more area for signal routing and removing the problems associated with capacitive stubs on edge connector traces associated with prior art designs. The method begins with creating a staggered plurality of blades or fingers. A plating bus is formed on these staggered blades by connecting a gold plating bus to one of the contact pads and then shorting together or connecting the signal lines via a shorting bus. The shorting bus is placed flush with the innermost edge of the edge connector well outside of the actual wipe area of the connectors. The board then undergoes a standard semi-additive process, as well as a final etch and subsequent gold plating. The shorting bar is then drilled out. Due to the placement of the shorting bar flush with the innermost edge of the edge connectors, the resultant vias do not occupy valuable signal routing area. Further, the drilling operation does not produce any capacitive stubs, thereby alleviating any cosmetic or performance problems associated with capacitive stubs, while not adding any additional time or cost to the board.

摘要翻译： 一种用于制造用于电路板的交错边缘连接器的廉价方法。 该方法具有成本效益，并且包括与现有技术相比的许多优点，包括允许更多的区域用于信号路由并且消除与现有技术设计相关联的边缘连接器迹线上的电容性短截线相关联的问题。 该方法开始于产生交错的多个刀片或手指。 通过将镀金母线连接到接触焊盘中的一个，然后通过短路总线短路或连接信号线，在这些交错的刀片上形成电镀母线。 短路总线与连接器的实际擦拭区域外部的边缘连接器的最内边缘齐平。 然后该板经历标准的半添加工艺，以及最终蚀刻和随后的镀金。 然后钻出短路棒。 由于短路棒与边缘连接器的最内边缘齐平，所产生的通孔不占用有价值的信号路由区域。 此外，钻孔操作不产生任何电容性短截线，从而减轻与电容性短截线相关的任何化妆品或性能问题，同时不向板增加任何额外的时间或成本。

公开(公告)号：US5729767A

公开(公告)日：1998-03-17

申请号：US319689

申请日：1994-10-07

申请人： Craig S. Jones ,  Victor K. Pecone ,  Jay Lory

发明人： Craig S. Jones ,  Victor K. Pecone ,  Jay Lory

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F11/22 ,  G06F11/267 ,  G06F11/34 ,  G06F13/00

CPC分类号： G06F11/1433 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0781 ,  G06F11/22 ,  G06F11/2236 ,  G06F11/006 ,  G06F11/2205 ,  G06F11/3476

摘要： A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot, the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

摘要翻译： 包括主机CPU，耦合到CPU的主PCI总线和耦合到主PCI总线的总线适配器的计算机系统，其中即使总线适配器不可操作，主机CPU也可以访问包含在总线适配器中的外围设备。 总线适配器包括PCI至PCI接口控制器，其包括用于耦合到主PCI总线的主PCI接口和用于耦合到辅助PCI总线的辅助PCI接口桥。 外部总线接口逻辑耦合在主PCI接口和辅助PCI接口之间，并且该接口逻辑耦合到各种外围设备，包括ROM /闪存和非易失性静态随机存取存储器（NVSRAM）。 根据本发明，在CPU上执行的主机实用程序可以访问外围设备，而不必访问辅助PCI总线。 因此，如果辅助PCI总线变得不可操作或本地处理器无法引导，则主机仍然可以访问外围设备中的存储器，因为外围接口有效地与辅助PCI总线和本地处理器分离。 本发明包括可以更新闪存的主机实用程序，从而提供用于在故障板上的损坏的闪存设备中恢复代码的成本有效且有效的机制。 这也使得在制造过程中首次对闪存进行编程。 本发明的系统和方法允许主机CPU访问NVRAM以获得事件故障信息，即使辅助PCI总线发生故障。

公开(公告)号：US5619728A

公开(公告)日：1997-04-08

申请号：US326570

申请日：1994-10-20

申请人： Craig S. Jones ,  Jay Lory ,  Victor K. Pecone

发明人： Craig S. Jones ,  Jay Lory ,  Victor K. Pecone

IPC分类号： G06F13/28 ,  H01J3/00

CPC分类号： G06F13/28

摘要： A peripheral resource controller such as a caching disk array controller is provided for controlling the transfer of data between a host bus and a peripheral resource, such as an array of hard disk drives. The peripheral resource controller includes a bus interface controller for providing an interface between the host bus and a local bus of the peripheral controller. The bus interface controller further includes a peripheral bus interface which accommodates accesses to a peripheral bus and a DMA controller for controlling direct memory access operations between a local memory of the peripheral controller and a system memory of the host computer. A DMA transfer list memory is coupled to the peripheral bus for storing DMA transfer information. The DMA controller fetches host and local address as well as block size information from the DMA transfer list memory to thereby effectuate DMA operations. In one specific implementation, a local processor of the peripheral controller loads the DMA transfer information into the DMA transfer list memory by causing the execution of one or more memory write cycles on the local bus. A local bus interface of the bus interface controller responds as a target and routes the data to a peripheral bus interface. The peripheral bus interface, which functions as a master of the peripheral bus, responsively effectuates corresponding cycles on the peripheral bus to write the DMA transfer information into the DMA transfer list memory.

摘要翻译： 提供诸如缓存磁盘阵列控制器之类的外围资源控制器，用于控制主机总线与诸如硬盘驱动器阵列的外围资源之间的数据传输。 外围资源控制器包括总线接口控制器，用于在主机总线和外围控制器的本地总线之间提供接口。 总线接口控制器还包括外围总线接口，其适应对外围总线的访问和用于控制外围控制器的本地存储器与主计算机的系统存储器之间的直接存储器访问操作的DMA控制器。 DMA传输列表存储器耦合到外围总线以存储DMA传输信息。 DMA控制器从DMA传输列表存储器中获取主机和本地地址以及块大小信息，从而实现DMA操作。 在一个具体实现中，外围控制器的本地处理器通过在本地总线上执行一个或多个存储器写周期来将DMA传输信息加载到DMA传输列表存储器中。 总线接口控制器的本地总线接口作为目标进行响应，并将数据路由到外设总线接口。 用作外设总线主机的外设总线接口响应于外设总线上的相应周期，将DMA传输信息写入DMA传输列表存储器。

公开(公告)号：US5571996A

公开(公告)日：1996-11-05

申请号：US375327

申请日：1995-01-17

申请人： N. Deepak Swamy ,  Victor K. Pecone ,  Darrell Slupek

发明人： N. Deepak Swamy ,  Victor K. Pecone ,  Darrell Slupek

IPC分类号： H05K1/02 ,  H05K7/14 ,  H05K1/18 ,  H05K1/14

CPC分类号： H05K1/0248 ,  H05K1/0228 ,  H05K7/1429 ,  H05K2201/044 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/09709 ,  H05K2201/09718

摘要： A circuit board is provided having a plurality of vias and uniformly spaced connector stubs arranged upon one or both outer surfaces of the control board. Sets of trace conductors are formed within the control board between the vias. The trace conductors are arranged in two planes within the control board, wherein trace conductors within one plane are laterally offset from trace conductors in the other plane. Laterally offset trace conductors allow close spacing of the trace conductor planes while maximizing the spacing between trace conductors and corresponding reference conductors also placed within the control board. Additionally, the trace conductors are serpentine-shaped when viewed from a perspective perpendicular to the planar surface of the control board. The serpentine shape, in conjunction with carefully controlled spacing between planes of trace conductors as well as between the trace conductor planes and reference conductors, provides high impedance trace conductors in a limited space area necessary to meet SCSI specifications.

摘要翻译： 设置有布置在控制板的一个或两个外表面上的多个通孔和均匀间隔的连接器短截线的电路板。 在通孔之间的控制板内形成导线组。 迹线导体布置在控制板内的两个平面中，其中一个平面内的迹线导体在另一个平面中横向偏离迹线导体。 横向偏移迹线导体允许迹线导体平面的紧密间隔，同时最大化迹线导体和也放置在控制板内的相应参考导体之间的间隔。 此外，当从垂直于控制板的平面表面的视角观察时，迹线导体是蛇形的。 蛇纹形状与跟踪导体的平面之间以及轨迹导体平面和参考导体之间的仔细控制的间距结合，在满足SCSI规范所需的有限空间区域内提供高阻抗迹线导体。

公开(公告)号：US5911084A

公开(公告)日：1999-06-08

申请号：US24719

申请日：1998-02-17

申请人： Craig S. Jones ,  Victor K. Pecone ,  Jay Lory

发明人： Craig S. Jones ,  Victor K. Pecone ,  Jay Lory

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F11/22 ,  G06F11/267 ,  G06F11/34 ,  G06F13/00

CPC分类号： G06F11/1433 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0781 ,  G06F11/22 ,  G06F11/2236 ,  G06F11/006 ,  G06F11/2205 ,  G06F11/3476

摘要： A computer system including a host CPU, a primary PCI bus coupled to the CPU, and a bus adapter coupled to the primary PCI bus, wherein the host CPU can access peripherals comprised in the bus adapter even when the bus adapter is inoperable. The bus adapter includes a PCI to PCI interface controller which includes a primary PCI interface for coupling to the primary PCI bus and a secondary PCI interface bridge for coupling to a secondary PCI bus. Peripheral bus interface logic is coupled between the primary PCI interface and the secondary PCI interface, and this interface logic couples to various peripheral devices, including ROM/Flash memory and non-volatile static random access memory (NVSRAM). According to the present invention, a host utility executing on the CPU can access the peripheral devices without having to access the secondary PCI bus. Thus, if the secondary PCI bus becomes inoperable or the local processor is unable to boot the host can still access the memory in the peripheral devices because the peripheral interface is effectively decoupled from the secondary PCI bus and the local processor. The present invention includes a host utility which can update the Flash memory, thereby providing a cost-effective and efficient mechanism for restoring code in a corrupted Flash device on a failed board. This also enables the Flash memory to be programmed for the first time during manufacturing. The system and method of the present invention allows the host CPU to access the NVRAM to obtain event failure information even if the secondary PCI bus has failed.

摘要翻译： 包括主机CPU，耦合到CPU的主PCI总线和耦合到主PCI总线的总线适配器的计算机系统，其中即使总线适配器不可操作，主机CPU也可以访问包含在总线适配器中的外围设备。 总线适配器包括PCI至PCI接口控制器，其包括用于耦合到主PCI总线的主PCI接口和用于耦合到辅助PCI总线的辅助PCI接口桥。 外部总线接口逻辑耦合在主PCI接口和辅助PCI接口之间，并且该接口逻辑耦合到各种外围设备，包括ROM /闪存和非易失性静态随机存取存储器（NVSRAM）。 根据本发明，在CPU上执行的主机实用程序可以访问外围设备，而不必访问辅助PCI总线。 因此，如果辅助PCI总线变得不可操作或本地处理器无法引导，则主机仍然可以访问外围设备中的存储器，因为外围接口有效地从辅助PCI总线和本地处理器分离。 本发明包括可以更新闪存的主机实用程序，从而提供用于在故障板上的损坏的闪存设备中恢复代码的成本有效且有效的机制。 这也使得在制造过程中首次对闪存进行编程。 本发明的系统和方法允许主机CPU访问NVRAM以获得事件故障信息，即使辅助PCI总线发生故障。

公开(公告)号：US5740386A

公开(公告)日：1998-04-14

申请号：US449501

申请日：1995-05-24

申请人： Kevin L. Miller ,  Victor K. Pecone

发明人： Kevin L. Miller ,  Victor K. Pecone

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022

摘要： A bus system is disclosed which includes first and second buses are coupled via an bus switch. The bus switch may be selectively turned on and off thus allowing the bus system to be electronically configured in a plurality of different configurations.

摘要翻译： 公开了一种总线系统，其包括通过总线开关耦合的第一和第二总线。 可以选择性地打开和关闭总线开关，从而允许总线系统以多种不同的配置电子地配置。

公开(公告)号：US5664119A

公开(公告)日：1997-09-02

申请号：US699016

申请日：1996-08-16

申请人： Kenneth L. Jeffries ,  Craig S. Jones ,  Victor K. Pecone

发明人： Kenneth L. Jeffries ,  Craig S. Jones ,  Victor K. Pecone

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4081

摘要： Apparatus and method for implementing a local proactive hot plug request/acknowledge scheme is disclosed. In a preferred embodiment, each hot pluggable device installable on a computer bus, such as a SCSI bus, is provided with a physical user interface comprising a mechanical request initiator, such as a button or two-position switch, for allowing a user to generate a hot swap request to a controller associated with the bus prior to actual installation of the device on, or removal of the device from, the bus. Upon receipt of the request, the controller determines whether the requested action may be performed, provides a visual indication of its determination to the user via an LED on the user interface and, if installation or removal is determined to be prudent, performs the hot installation/removal in an orderly manner so as not to adversely affect ongoing system operations.

摘要翻译： 公开了用于实现本地主动式热插拔请求/确认方案的装置和方法。 在优选实施例中，可安装在诸如SCSI总线的计算机总线上的每个热插拔设备都设置有物理用户界面，其包括诸如按钮或两位置开关的机械请求发起者，用于允许用户生成 在将设备实际安装在总线上或从总线移除设备之前，向与总线相关联的控制器的热交换请求。 在接收到请求时，控制器确定是否可以执行请求的动作，通过用户界面上的LED向用户提供其确定的可视指示，并且如果确定安全或删除是谨慎的，则执行热安装 /有秩序地移除，以免对正在进行的系统操作产生不利影响。