公开(公告)号：US5567295A

公开(公告)日：1996-10-22

申请号：US180175

申请日：1994-01-11

申请人： Deepak N. Swamy ,  Victor K. Pecone

发明人： Deepak N. Swamy ,  Victor K. Pecone

IPC分类号： C07K14/71 ,  G01N33/566 ,  G01N33/74 ,  H05K1/11 ,  H05K3/00 ,  H05K3/24 ,  C25D5/02

CPC分类号： H05K3/242 ,  C25D17/005 ,  H05K1/117 ,  H05K2201/094 ,  H05K2203/175 ,  H05K3/0047 ,  H05K3/0052

摘要： An inexpensive method for fabricating a staggered edge connector for a circuit board. The method is cost effective and includes numerous advantages over the prior art, including allowing more area for signal routing and removing the problems associated with capacitive stubs on edge connector traces associated with prior art designs. The method begins with creating a staggered plurality of blades or fingers. A plating bus is formed on these staggered blades by connecting a gold plating bus to one of the contact pads and then shorting together or connecting the signal lines via a shorting bus. The shorting bus is placed flush with the innermost edge of the edge connector well outside of the actual wipe area of the connectors. The board then undergoes a standard semi-additive process, as well as a final etch and subsequent gold plating. The shorting bar is then drilled out. Due to the placement of the shorting bar flush with the innermost edge of the edge connectors, the resultant vias do not occupy valuable signal routing area. Further, the drilling operation does not produce any capacitive stubs, thereby alleviating any cosmetic or performance problems associated with capacitive stubs, while not adding any additional time or cost to the board.

摘要翻译： 一种用于制造用于电路板的交错边缘连接器的廉价方法。 该方法具有成本效益，并且包括与现有技术相比的许多优点，包括允许更多的区域用于信号路由并且消除与现有技术设计相关联的边缘连接器迹线上的电容性短截线相关联的问题。 该方法开始于产生交错的多个刀片或手指。 通过将镀金母线连接到接触焊盘中的一个，然后通过短路总线短路或连接信号线，在这些交错的刀片上形成电镀母线。 短路总线与连接器的实际擦拭区域外部的边缘连接器的最内边缘齐平。 然后该板经历标准的半添加工艺，以及最终蚀刻和随后的镀金。 然后钻出短路棒。 由于短路棒与边缘连接器的最内边缘齐平，所产生的通孔不占用有价值的信号路由区域。 此外，钻孔操作不产生任何电容性短截线，从而减轻与电容性短截线相关的任何化妆品或性能问题，同时不向板增加任何额外的时间或成本。

公开(公告)号：US5576519A

公开(公告)日：1996-11-19

申请号：US409289

申请日：1995-03-23

申请人： Deepak N. Swamy

发明人： Deepak N. Swamy

IPC分类号： B23K35/02 ,  H05K3/00 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H05K3/46 ,  H05K1/14

CPC分类号： H05K3/462 ,  B23K35/0222 ,  H05K3/3436 ,  H05K3/368 ,  B23K35/025 ,  H05K1/0272 ,  H05K2201/09536 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2203/0376 ,  H05K2203/043 ,  H05K2203/0554 ,  H05K2203/0568 ,  H05K3/0032 ,  H05K3/3484 ,  H05K3/4069 ,  H05K3/4623 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49222

摘要： An interconnect sheet for connecting multiple layers of a circuit board for the manufacture of high interconnect density PWBs. The interconnect sheet preferably comprises an area array grid of 0.003 inch solder columns having a 0.006 inch pitch. The interconnect sheet is preferably used to attach two or more multi-layer boards by placing one sheet at every interconnect surface. This interconnect mechanism has an advantage of redundancy of contact and therefore lower susceptibility to failure than other methods. The interconnect sheet of the present invention also offers a large tolerance for registration error without shorting adjacent pads. The preferred method of fabrication of the interconnect sheet begins with creating equally spaced holes through a 0.5 ounce double sided laminate comprising a dielectric sheet and copper plates on either side of the dielectric. These holes are filled with solder paste and the sheet undergoes a baking process to shrink the paste. The remaining copper is then etched away using an alkaline etcher. The solder essentially acts as its own etch resist and thus remains. The solder is then reflowed causing it to ball, thus forming an interconnect sheet comprising a dielectric with a plurality of solder balls arranged throughout the dielectric.

摘要翻译： 用于连接多层电路板以用于制造高互连密度PWB的互连片。 互连片优选地包括具有0.006英寸间距的0.003英寸焊料柱的面阵列栅格。 互连片优选用于通过在每个互连表面放置一个片来附接两个或更多个多层板。 这种互连机构具有接触冗余的优点，因此比其它方法具有较低的故障敏感性。 本发明的互连片材还提供了对配准误差的大容差，而不会使邻近的衬垫短路。 制造互连片的首选方法是从电介质片和电介质两侧的铜板上形成等距隔开的孔，通过0.5盎司双面层压板。 这些孔填充有焊膏，并且片材经历烘烤处理以收缩糊料。 然后使用碱蚀刻器将剩余的铜蚀刻掉。 焊料基本上充当其自身的抗蚀剂，因此保留。 然后焊料回流使其成球，从而形成包括电介质的互连片，多个焊球布置在整个电介质中。

公开(公告)号：US5276955A

公开(公告)日：1994-01-11

申请号：US868531

申请日：1992-04-14

申请人： David B. Noddin ,  Robin E. Gorrell ,  William G. Petefish ,  Kevin L. Stumpe ,  Boydd Piper ,  Deepak N. Swamy ,  Jimmy Leong ,  Michael R. Leaf

发明人： David B. Noddin ,  Robin E. Gorrell ,  William G. Petefish ,  Kevin L. Stumpe ,  Boydd Piper ,  Deepak N. Swamy ,  Jimmy Leong ,  Michael R. Leaf

IPC分类号： H01L21/48 ,  H05K3/32 ,  H05K3/36 ,  H05K3/46

CPC分类号： H05K3/462 ,  H01L21/4857 ,  H05K3/368 ,  H05K1/0272 ,  H05K2201/0379 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0278 ,  H05K3/325 ,  H05K3/328 ,  H05K3/4623 ,  Y10T29/49004 ,  Y10T29/49128

摘要： A method and apparatus for manufacturing large area multilayer interconnects for electronic substrates and circuit boards uses high density area array interconnections that are created by solid state diffusion. Two or more pretested subsections are electrically and mechanically joined together to simultaneously form a multilayer substrate without employing a flow-type connection where the conductive interconnect material is entirely in a liquid phase at some point during the joining process. Each substrate is comprised of a planar dielectric substrate having a plurality of conductive layers. On at least one surface of the substrate a conductive pad lay is formed having a plurality of interconnect pads. The interconnect pads are positioned at a uniform height above the surface of the dielectric substrate and include a base metal layer, a top metal layer with at least one of the conductive pad layers have a donor metal disposed on top of the top metal layer. When the conductive pad layers of two or more subsections are aligned and stacked together, the interconnect pads can be mechanically and electrically joined together using solid state diffusion to join the donor metal layer and the top metal layer to form an area array interconnection without bonding the surrounding dielectric substrate.

摘要翻译： 用于制造用于电子基板和电路板的大面积多层互连的方法和装置使用由固态扩散产生的高密度区域阵列互连。 两个或更多个预测试的子部分电连接和机械连接在一起，以同时形成多层基板，而不采用流动型连接，其中导电互连材料在接合过程中的某一点处完全处于液相。 每个衬底由具有多个导电层的平面电介质衬底组成。 在衬底的至少一个表面上形成具有多个互连衬垫的导电衬垫。 互连焊盘位于电介质基板的表面上方的均匀高度处，并且包括基底金属层，具有至少一个导电焊盘层的顶部金属层具有设置在顶部金属层顶部的施主金属。 当两个或更多个子部分的导电焊盘层对准并堆叠在一起时，可以使用固态扩散将互连焊盘机械地和电连接在一起，以连接施主金属层和顶部金属层，以形成区域阵列互连，而不粘合 周围电介质基板。

公开(公告)号：US5424492A

公开(公告)日：1995-06-13

申请号：US178078

申请日：1994-01-06

申请人： Robert B. Petty ,  Michael D. Ohlinger ,  Deepak N. Swamy ,  Joseph Mallory

发明人： Robert B. Petty ,  Michael D. Ohlinger ,  Deepak N. Swamy ,  Joseph Mallory

IPC分类号： H05K1/02 ,  H05K1/11 ,  H05K1/00

CPC分类号： H05K1/115 ,  H05K1/114 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2924/01039 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K2201/09227 ,  H05K2201/10734

摘要： An optimal routing methodology for routing high I/O density packages which minimizes the number of PCB layers required. One feature of this routing methodology comprises treating respective I/O that are routed at the top layer of the package as surface mount technology (SMT) pads without dropping vias within the BGA grid, as is commonplace in the industry. This facilitates the use of fewer escapes and allows for more efficient use of the available space. Signal lines on the top layer of the package which must be routed to other layers of the PCB are connected to vias outside of the area of local high signal density on the printed circuit board. The placement of vias outside the area of local high density, i.e., in a depopulated area, reduces the number of layers necessary in the PCB to properly route the signals. This placement also facilitates the use of filtering capacitors to meet EMI requirements. In addition, all voltage pins are placed on the innermost or outermost grids and have clearanced vias. The device is also preferably placed at the beginning or at the end of the bus to maximize the routing efficiency.

摘要翻译： 用于布线高I / O密度封装的最佳路由方法，其最小化所需的PCB层数量。 该路由选择方法的一个特征包括处理作为表面贴装技术（SMT）焊盘而在封装顶层布线的相应I / O，而不会在BGA网格内掉下通孔，这在工业中是常见的。 这有助于使用更少的转义，并允许更有效地使用可用空间。 封装顶层上必须连接到PCB其他层的信号线连接到印刷电路板上局部高信号密度区域之外的通孔。 在局部高密度区域（即，在人口稀少的区域）之外的通孔的放置减少了PCB中所需的层数以适当地路由信号。 该放置还有助于使用滤波电容器来满足EMI要求。 此外，所有电压引脚都放置在最内侧或最外侧的栅格上，并具有通孔。 该装置还优选地放置在总线的开始或结束处以最大化路由效率。

公开(公告)号：US5392980A

公开(公告)日：1995-02-28

申请号：US175030

申请日：1993-12-29

申请人： Deepak N. Swamy ,  Scott Estes ,  James Bell

发明人： Deepak N. Swamy ,  Scott Estes ,  James Bell

IPC分类号： H01L21/48 ,  H01L23/498 ,  H05K3/12 ,  H01L21/60

CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/49816 ,  H05K3/1216 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/1532 ,  H01L2924/181

摘要： A rework process for ball grid array (BGA) packages which allows for reuse of devices that have been removed for lack of integrity of solder interconnections. The process uses a rework tool which comprises a plate including one or more depressions corresponding to the contours of inverted BGA packages. A BGA package to be reworked is placed in a respective depression with what remains of the original solder ball grid facing upward. The residual solder balls are wicked away, thus leaving the BGA package with the pads that the solder balls were attached to being exposed. A stencil with BGA patterns punched into it is then placed over the rework tool and solder paste is screened onto the rework tool so that the solder is deposited on the BGA pads via the openings in the stencil. The entire fixture is then subjected to a reflow process to cause the solder to ball up during this process. After the reflow process has completed, the stencil is removed, leaving behind a ball grid array similar to that found in the original package.

摘要翻译： 用于球栅阵列（BGA）封装的返工工艺，其允许对由于缺乏焊接互连的完整性而被去除的器件的再利用。 该方法使用返工工具，其包括板，该板包括对应于反向BGA封装的轮廓的一个或多个凹陷。 要重新加工的BGA封装被放置在相应的凹部中，原始焊球栅格的剩余物面向上。 剩余的焊球被弄脏，因此留下BGA封装与焊球附着的焊盘露出。 然后将穿过其中的BGA图案的模板放置在返工工具上，并将焊膏筛选到返工工具上，使得焊料通过模板中的开口沉积在BGA焊盘上。 然后将整个固定装置进行回流处理，以在该过程中使焊料起球。 在回流过程完成后，模板被去除，留下与原始封装中相似的球栅阵列。

公开(公告)号：US5987553A

公开(公告)日：1999-11-16

申请号：US935127

申请日：1997-09-22

申请人： Deepak N. Swamy ,  Andrew W. Moore

发明人： Deepak N. Swamy ,  Andrew W. Moore

IPC分类号： G06F1/18 ,  G06F13/38

CPC分类号： G06F1/183

摘要： A computer system includes a motherboard to which a selected one of various processor boards can be coupled via an adaptor. The boards include a CPU and a heat transfer member. The adaptor includes core logic such as a Northbridge module and power control circuitry. The adaptor is pin connectable to the motherboard and the various processor boards are each pin connectable to the adaptor. Alternatively, the adaptor and processor boards can be replaced with a processor module including features of the processor boards and the adaptor. The processor module is also pin connectable to the motherboard at the same connection used by the adaptor.

摘要翻译： 计算机系统包括主板，多个处理器板中的所选择的一个可经由适配器耦合到主板。 这些板包括CPU和传热构件。 适配器包括核心逻辑，如北桥模块和电源控制电路。 适配器可针脚连接到主板，各个处理器板的每个针可连接到适配器。 或者，可以用包括处理器板和适配器的特征的处理器模块来替换适配器和处理器板。 处理器模块也可以通过适配器使用的相同连接引脚连接到主板。

公开(公告)号：US5456004A

公开(公告)日：1995-10-10

申请号：US177055

申请日：1994-01-04

申请人： Deepak N. Swamy

发明人： Deepak N. Swamy

IPC分类号： B23K35/02 ,  H05K3/00 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H05K3/46 ,  H01K3/10

CPC分类号： H05K3/462 ,  B23K35/0222 ,  H05K3/3436 ,  H05K3/368 ,  B23K35/025 ,  H05K1/0272 ,  H05K2201/09536 ,  H05K2201/10378 ,  H05K2201/10424 ,  H05K2203/0376 ,  H05K2203/043 ,  H05K2203/0554 ,  H05K2203/0568 ,  H05K3/0032 ,  H05K3/3484 ,  H05K3/4069 ,  H05K3/4623 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49222

摘要： An interconnect sheet for connecting multiple layers of a circuit board for the manufacture of high interconnect density PWBs. The interconnect sheet preferably comprises an area array grid of 0.003 inch solder columns having a 0.006 inch pitch. The interconnect sheet is preferably used to attach two or more multi-layer boards by placing one sheet at every interconnect surface. This interconnect mechanism has an advantage of redundancy of contact and therefore lower susceptibility to failure than other methods. The interconnect sheet of the present invention also offers a large tolerance for registration error without shorting adjacent pads. The preferred method of fabrication of the interconnect sheet begins with creating equally spaced holes through a 0.5 ounce double sided laminate comprising a dielectric sheet and copper plates on either side of the dielectric. These holes are filled with solder paste and the sheet undergoes a baking process to shrink the paste. The remaining copper is then etched away using an alkaline etcher. The solder essentially acts as its own etch resist and thus remains. The solder is then reflowed causing it to ball, thus forming an interconnect sheet comprising a dielectric with a plurality of solder balls arranged throughout the dielectric.

摘要翻译： 用于连接多层电路板以用于制造高互连密度PWB的互连片。 互连片优选地包括具有0.006英寸间距的0.003英寸焊料柱的面阵列栅格。 互连片优选用于通过在每个互连表面放置一个片来附接两个或更多个多层板。 这种互连机构具有接触冗余的优点，因此比其它方法具有较低的故障敏感性。 本发明的互连片材还提供了对配准误差的大容差，而不会使邻近的衬垫短路。 制造互连片的首选方法是从电介质片和电介质两侧的铜板上形成等距隔开的孔，通过0.5盎司双面层压板。 这些孔填充有焊膏，并且片材经历烘烤处理以收缩糊料。 然后使用碱蚀刻器将剩余的铜蚀刻掉。 焊料基本上充当其自身的抗蚀剂，因此保留。 然后焊料回流使其成球，从而形成包括电介质的互连片，多个焊球布置在整个电介质中。